From dfbfc57d78b74084ede5aa3ff8b380d64cb4d27e Mon Sep 17 00:00:00 2001 From: Misha Brukman Date: Wed, 16 Jul 2003 20:30:40 +0000 Subject: [PATCH] Fixed the number translation scheme for the integer condition code registers: it now works in instructions which require a 2-bit or 3-bit INTcc code. Incidentally, that means that the representation of INTcc registers is now the same in both integer and FP instructions. Thus, code became much simpler and cleaner. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7185 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/SparcV9/SparcV9CodeEmitter.cpp | 39 +++++------------------ lib/Target/SparcV9/SparcV9CodeEmitter.h | 1 - 2 files changed, 8 insertions(+), 32 deletions(-) diff --git a/lib/Target/SparcV9/SparcV9CodeEmitter.cpp b/lib/Target/SparcV9/SparcV9CodeEmitter.cpp index bc638c337a3..d7ca70c2eff 100644 --- a/lib/Target/SparcV9/SparcV9CodeEmitter.cpp +++ b/lib/Target/SparcV9/SparcV9CodeEmitter.cpp @@ -327,22 +327,6 @@ void SparcV9CodeEmitter::emitWord(unsigned Val) { } } -bool SparcV9CodeEmitter::isFPInstr(MachineInstr &MI) { - for (unsigned i = 0, e = MI.getNumOperands(); i < e; ++i) { - const MachineOperand &MO = MI.getOperand(i); - if (MO.isPhysicalRegister()) { - unsigned fakeReg = MO.getReg(), realReg, regClass, regType; - regType = TM.getRegInfo().getRegType(fakeReg); - // At least map fakeReg into its class - // fakeReg = TM.getRegInfo().getClassRegNum(fakeReg, regClass); - if (regType == UltraSparcRegInfo::FPSingleRegType || - regType == UltraSparcRegInfo::FPDoubleRegType) - return true; - } - } - return false; -} - unsigned SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg, MachineInstr &MI) { @@ -386,21 +370,13 @@ SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg, return fakeReg; } case UltraSparcRegInfo::IntCCRegClassID: { - /* xcc, icc, ccr */ - static const unsigned FPInstrIntCCReg[] = { 6, 4, 2 }; - static const unsigned IntInstrIntCCReg[] = { 2, 0, 2 }; + /* xcc, icc, ccr */ + static const unsigned IntCCReg[] = { 6, 4, 2 }; - if (isFPInstr(MI)) { - assert(fakeReg < sizeof(FPInstrIntCCReg)/sizeof(FPInstrIntCCReg[0]) - && "FP CC register out of bounds for FPInstr IntCCReg map"); - DEBUG(std::cerr << "FP instr, IntCC reg: " << FPInstrIntCCReg[fakeReg] << "\n"); - return FPInstrIntCCReg[fakeReg]; - } else { - assert(fakeReg < sizeof(IntInstrIntCCReg)/sizeof(IntInstrIntCCReg[0]) - && "Int CC register out of bounds for IntInstr IntCCReg map"); - DEBUG(std::cerr << "FP instr, IntCC reg: " << IntInstrIntCCReg[fakeReg] << "\n"); - return IntInstrIntCCReg[fakeReg]; - } + assert(fakeReg < sizeof(IntCCReg)/sizeof(IntCCReg[0]) + && "CC register out of bounds for IntCCReg map"); + DEBUG(std::cerr << "IntCC reg: " << IntCCReg[fakeReg] << "\n"); + return IntCCReg[fakeReg]; } case UltraSparcRegInfo::FloatCCRegClassID: { /* These are laid out %fcc0 - %fcc3 => 0 - 3, so are correct */ @@ -580,7 +556,8 @@ int64_t SparcV9CodeEmitter::getMachineOpValue(MachineInstr &MI, unsigned fakeReg = MO.getAllocatedRegNum(); unsigned realRegByClass = getRealRegNum(fakeReg, MI); DEBUG(std::cerr << MO << ": Reg[" << std::dec << fakeReg << "] => " - << realRegByClass << "\n"); + << realRegByClass << " (LLC: " + << TM.getRegInfo().getUnifiedRegName(fakeReg) << ")\n"); rv = realRegByClass; } else if (MO.isImmediate()) { rv = MO.getImmedValue(); diff --git a/lib/Target/SparcV9/SparcV9CodeEmitter.h b/lib/Target/SparcV9/SparcV9CodeEmitter.h index ca365d06848..ebadc379d9f 100644 --- a/lib/Target/SparcV9/SparcV9CodeEmitter.h +++ b/lib/Target/SparcV9/SparcV9CodeEmitter.h @@ -47,7 +47,6 @@ private: void emitBasicBlock(MachineBasicBlock &MBB); void* getGlobalAddress(GlobalValue *V, MachineInstr &MI, bool isPCRelative); - bool isFPInstr(MachineInstr &MI); unsigned getRealRegNum(unsigned fakeReg, MachineInstr &MI); inline void emitFarCall(uint64_t Addr);