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DAG combiner fix for rotates. Previously the outer-most condition checks
for ROTL availability. This prevents it from forming ROTR for targets that has ROTR only. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29997 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1160,29 +1160,46 @@ SDOperand DAGCombiner::visitOR(SDNode *N) {
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// check for rotl, rotr
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if (N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SRL &&
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N0.getOperand(0) == N1.getOperand(0) &&
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TLI.isOperationLegal(ISD::ROTL, VT) && TLI.isTypeLegal(VT)) {
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TLI.isTypeLegal(VT)) {
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bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT);
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bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT);
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if (HasROTL || HasROTR) {
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// fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
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// fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
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if (N0.getOperand(1).getOpcode() == ISD::Constant &&
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N1.getOperand(1).getOpcode() == ISD::Constant) {
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uint64_t c1val = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
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uint64_t c2val = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
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if ((c1val + c2val) == OpSizeInBits)
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return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1));
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if (HasROTL)
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return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0),
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N0.getOperand(1));
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else
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return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0),
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N1.getOperand(1));
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}
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// fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
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// fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
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if (N1.getOperand(1).getOpcode() == ISD::SUB &&
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N0.getOperand(1) == N1.getOperand(1).getOperand(1))
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if (ConstantSDNode *SUBC =
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dyn_cast<ConstantSDNode>(N1.getOperand(1).getOperand(0)))
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if (SUBC->getValue() == OpSizeInBits)
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return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1));
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if (HasROTL)
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return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0),
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N0.getOperand(1));
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else
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return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0),
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N1.getOperand(1));
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// fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
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// fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
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if (N0.getOperand(1).getOpcode() == ISD::SUB &&
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N1.getOperand(1) == N0.getOperand(1).getOperand(1))
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if (ConstantSDNode *SUBC =
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dyn_cast<ConstantSDNode>(N0.getOperand(1).getOperand(0)))
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if (SUBC->getValue() == OpSizeInBits) {
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if (TLI.isOperationLegal(ISD::ROTR, VT) && TLI.isTypeLegal(VT))
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if (SUBC->getValue() == OpSizeInBits)
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if (HasROTR)
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return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0),
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N1.getOperand(1));
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else
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