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fix PR7311 by avoiding breaking casts when a bitcast from scalar->vector
is involved. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108117 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2007,6 +2007,14 @@ unsigned CastInst::isEliminableCastPair(
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{ 5, 5, 5, 6, 6, 5, 5, 6, 6,11, 5, 1 }, // BitCast -+
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{ 5, 5, 5, 6, 6, 5, 5, 6, 6,11, 5, 1 }, // BitCast -+
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};
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};
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// If either of the casts are a bitcast from scalar to vector, disallow the
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// merging.
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if ((firstOp == Instruction::BitCast &&
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isa<VectorType>(SrcTy) != isa<VectorType>(MidTy)) ||
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(secondOp == Instruction::BitCast &&
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isa<VectorType>(MidTy) != isa<VectorType>(DstTy)))
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return 0; // Disallowed
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int ElimCase = CastResults[firstOp-Instruction::CastOpsBegin]
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int ElimCase = CastResults[firstOp-Instruction::CastOpsBegin]
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[secondOp-Instruction::CastOpsBegin];
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[secondOp-Instruction::CastOpsBegin];
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switch (ElimCase) {
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switch (ElimCase) {
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@ -638,3 +638,14 @@ define <4 x i32> @test62(<3 x float> %call4) nounwind {
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; CHECK-NEXT: ret
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; CHECK-NEXT: ret
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}
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}
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; PR7311 - Don't create invalid IR on scalar->vector cast.
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define <2 x float> @test63(i64 %tmp8) nounwind {
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entry:
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%a = bitcast i64 %tmp8 to <2 x i32>
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%vcvt.i = uitofp <2 x i32> %a to <2 x float>
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ret <2 x float> %vcvt.i
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; CHECK: @test63
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; CHECK: bitcast
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; CHECK: uitofp
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}
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