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some call work
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22303 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -119,7 +119,8 @@ static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
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std::vector<SDOperand>
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V8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
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{
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//FIXME
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static const unsigned IncomingArgRegs[] =
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{ V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5 };
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std::vector<SDOperand> ArgValues;
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MachineFunction &MF = DAG.getMachineFunction();
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@ -127,6 +128,68 @@ V8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
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MachineBasicBlock& BB = MF.front();
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unsigned ArgNo = 0;
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unsigned ArgOffset = 92;
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for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
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I != E; ++I, ++ArgNo) {
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MVT::ValueType VT = getValueType(I->getType());
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SDOperand argt;
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if (ArgNo < 6) {
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switch(VT) {
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default:
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std::cerr << "Unknown Type " << VT << "\n";
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abort();
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case MVT::f64:
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case MVT::i64:
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//FIXME: figure out the build pair thing
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assert(0 && "doubles and longs not supported yet");
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case MVT::f32:
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argt = DAG.getCopyFromReg(AddLiveIn(MF, IncomingArgRegs[ArgNo],
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MVT::i32),
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VT, DAG.getRoot());
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//copy out of Int reg
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argt = DAG.getNode(ISD::FP_TO_UINT, MVT::f32, argt);
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break;
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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argt = DAG.getCopyFromReg(AddLiveIn(MF, IncomingArgRegs[ArgNo],
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getRegClassFor(MVT::i32)),
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VT, DAG.getRoot());
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if (VT != MVT::i32)
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argt = DAG.getNode(ISD::TRUNCATE, VT, argt);
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break;
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}
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DAG.setRoot(argt.getValue(1));
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} else {
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//stack passed
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switch(VT) {
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default:
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std::cerr << "Unknown Type " << VT << "\n";
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abort();
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case MVT::f64:
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case MVT::i64:
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//FIXME: figure out the build pair thing
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assert(0 && "doubles and longs not supported yet");
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case MVT::f32:
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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// Create the frame index object for this incoming parameter...
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int FI = MFI->CreateFixedObject(4, ArgOffset);
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argt = DAG.getLoad(VT,
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DAG.getEntryNode(),
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DAG.getFramIndex(FI, MVT::i32),
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DAG.getSrcValue(NULL));
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ArgOffset += 4;
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break;
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}
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ArgValues.push_back(argt);
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}
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}
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//return the arguments
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return ArgValues;
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}
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@ -119,7 +119,8 @@ static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
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std::vector<SDOperand>
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V8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
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{
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//FIXME
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static const unsigned IncomingArgRegs[] =
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{ V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5 };
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std::vector<SDOperand> ArgValues;
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MachineFunction &MF = DAG.getMachineFunction();
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@ -127,6 +128,68 @@ V8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
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MachineBasicBlock& BB = MF.front();
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unsigned ArgNo = 0;
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unsigned ArgOffset = 92;
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for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
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I != E; ++I, ++ArgNo) {
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MVT::ValueType VT = getValueType(I->getType());
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SDOperand argt;
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if (ArgNo < 6) {
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switch(VT) {
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default:
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std::cerr << "Unknown Type " << VT << "\n";
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abort();
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case MVT::f64:
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case MVT::i64:
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//FIXME: figure out the build pair thing
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assert(0 && "doubles and longs not supported yet");
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case MVT::f32:
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argt = DAG.getCopyFromReg(AddLiveIn(MF, IncomingArgRegs[ArgNo],
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MVT::i32),
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VT, DAG.getRoot());
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//copy out of Int reg
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argt = DAG.getNode(ISD::FP_TO_UINT, MVT::f32, argt);
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break;
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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argt = DAG.getCopyFromReg(AddLiveIn(MF, IncomingArgRegs[ArgNo],
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getRegClassFor(MVT::i32)),
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VT, DAG.getRoot());
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if (VT != MVT::i32)
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argt = DAG.getNode(ISD::TRUNCATE, VT, argt);
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break;
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}
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DAG.setRoot(argt.getValue(1));
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} else {
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//stack passed
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switch(VT) {
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default:
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std::cerr << "Unknown Type " << VT << "\n";
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abort();
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case MVT::f64:
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case MVT::i64:
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//FIXME: figure out the build pair thing
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assert(0 && "doubles and longs not supported yet");
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case MVT::f32:
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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// Create the frame index object for this incoming parameter...
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int FI = MFI->CreateFixedObject(4, ArgOffset);
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argt = DAG.getLoad(VT,
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DAG.getEntryNode(),
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DAG.getFramIndex(FI, MVT::i32),
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DAG.getSrcValue(NULL));
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ArgOffset += 4;
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break;
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}
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ArgValues.push_back(argt);
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}
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}
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//return the arguments
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return ArgValues;
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}
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