6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-13 20:32:21 +00:00
Code Issues Projects Releases Wiki Activity

ARM sched model: Add preload instructions

Browse Source 
Reapply 183261.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183425 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Arnold Schwaighofer 2013-06-06 17:26:12 +00:00
parent 54154f3bf1
commit e022a6b0f4
1 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
lib/Target/ARM/ARMInstrInfo.td
View File

@ -1780,7 +1780,8 @@ multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
!strconcat(opc, "\t$addr"),
[(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
[(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>,
Sched<[WritePreLd]> {
bits<4> Rt;
bits<17> addr;
let Inst{31-26} = 0b111101;
@ -1796,7 +1797,8 @@ multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
!strconcat(opc, "\t$shift"),
[(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
[(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>,
Sched<[WritePreLd]> {
bits<17> shift;
let Inst{31-26} = 0b111101;
let Inst{25} = 1; // 1 for register form