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Doubleword Shift Left Logical Plus 32

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Mips shift instructions DSLL, DSRL and DSRA are transformed into
DSLL32, DSRL32 and DSRA32 respectively if the shift amount is between
32 and 63

Here is a description of DSLL:

Purpose: Doubleword Shift Left Logical Plus 32
To execute a left-shift of a doubleword by a fixed amount--32 to 63 bits

Description: GPR[rd] <- GPR[rt] << (sa+32)

The 64-bit doubleword contents of GPR rt are shifted left, inserting
 zeros into the emptied bits; the result is placed in
GPR rd. The bit-shift amount in the range 0 to 31 is specified by sa.

This patch implements the direct object output of these instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160277 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jack Carter
2012-07-16 15:14:51 +00:00
parent 694fbf1777
commit e035f65b16
5 changed files with 102 additions and 1 deletions
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22
lib/Target/Mips/MipsAsmPrinter.cpp
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@@ -13,9 +13,10 @@
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "mips-asm-printer"
#include "MipsAsmPrinter.h"
#include "Mips.h"
#include "MipsAsmPrinter.h"
#include "MipsInstrInfo.h"
#include "MipsMCInstLower.h"
#include "InstPrinter/MipsInstPrinter.h"
#include "MCTargetDesc/MipsBaseInfo.h"
#include "llvm/ADT/SmallString.h"
@@ -57,6 +58,25 @@ void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
return;
}
// Direct object specific instruction lowering
if (!OutStreamer.hasRawTextSupport())
switch (MI->getOpcode()) {
case Mips::DSLL:
case Mips::DSRL:
case Mips::DSRA:
assert(MI->getNumOperands() == 3 &&
"Invalid no. of machine operands for shift!");
assert(MI->getOperand(2).isImm());
int64_t Shift = MI->getOperand(2).getImm();
if (Shift > 31) {
MCInst TmpInst0;
MCInstLowering.LowerLargeShift(MI, TmpInst0, Shift - 32);
OutStreamer.EmitInstruction(TmpInst0);
return;
}
break;
}
MachineBasicBlock::const_instr_iterator I = MI;
MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();