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Fixed a bug about disassembling AArch64 post-index load/store single element instructions.

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ie. echo "0x00 0x04 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble
    echo "0x00 0x00 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble
will be disassembled into the same instruction st1 {v0b}[0], [x0], x0.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195591 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hao Liu
2013-11-25 01:53:26 +00:00
parent da99801ab4
commit e04ed6b8b1
2 changed files with 21 additions and 16 deletions
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23
lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
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@@ -1117,7 +1117,9 @@ static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst &Inst, unsigned Insn,
bool Is64bitVec = false;
bool IsLoadDup = false;
bool IsLoad = false;
unsigned TransferBytes = 0; // The total number of bytes transferred.
// The total number of bytes transferred.
// TransferBytes = NumVecs * OneLaneBytes
unsigned TransferBytes = 0;
unsigned NumVecs = 0;
unsigned Opc = Inst.getOpcode();
switch (Opc) {
@@ -1511,17 +1513,20 @@ static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst &Inst, unsigned Insn,
unsigned Q = fieldFromInstruction(Insn, 30, 1);
unsigned S = fieldFromInstruction(Insn, 10, 3);
unsigned lane = 0;
switch (NumVecs) {
case 1:
lane = (Q << 3) & S;
// Calculate the number of lanes by number of vectors and transfered bytes.
// NumLanes = 16 bytes / bytes of each lane
unsigned NumLanes = 16 / (TransferBytes / NumVecs);
switch (NumLanes) {
case 16: // A vector has 16 lanes, each lane is 1 bytes.
lane = (Q << 3) | S;
break;
case 2:
lane = (Q << 2) & (S >> 1);
break;
case 3:
lane = (Q << 1) & (S >> 2);
case 8:
lane = (Q << 2) | (S >> 1);
break;
case 4:
lane = (Q << 1) | (S >> 2);
break;
case 2:
lane = Q;
break;
}