diff --git a/lib/Target/X86/FloatingPoint.cpp b/lib/Target/X86/FloatingPoint.cpp index b8934769965..8673fd61cdb 100644 --- a/lib/Target/X86/FloatingPoint.cpp +++ b/lib/Target/X86/FloatingPoint.cpp @@ -603,55 +603,3 @@ void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) { I = MBB->erase(I)-1; // Remove the pseudo instruction delete MI; } - -namespace { - struct FPK : public MachineFunctionPass { - virtual const char *getPassName() const { return "X86 FP Killer"; } - virtual bool runOnMachineFunction(MachineFunction &MF); - virtual void getAnalysisUsage(AnalysisUsage &AU) const { - AU.addPreserved(); - AU.addRequired(); - AU.addPreservedID(PHIEliminationID); - AU.addRequiredID(PHIEliminationID); - MachineFunctionPass::getAnalysisUsage(AU); - } - }; -} - -FunctionPass *llvm::createX86FloatingPointKillerPass() { return new FPK(); } - -bool FPK::runOnMachineFunction(MachineFunction &MF) { - const TargetInstrInfo& tii = MF.getTarget().getInstrInfo();; - LiveVariables &LV = getAnalysis(); - - for (MachineFunction::iterator - mbbi = MF.begin(), mbbe = MF.end(); mbbi != mbbe; ++mbbi) { - MachineBasicBlock& mbb = *mbbi; - MachineBasicBlock::reverse_iterator mii = mbb.rbegin(); - // rewind to the last non terminating instruction - while (mii != mbb.rend() && tii.isTerminatorInstr((*mii)->getOpcode())) - ++mii; - - // add implicit def for all virtual floating point registers so that - // they are spilled at the end of each basic block, since our - // register stackifier doesn't handle them otherwise. - MachineInstr* instr = BuildMI(X86::IMPLICIT_DEF, 7) - .addReg(X86::FP6, MOTy::Def) - .addReg(X86::FP5, MOTy::Def) - .addReg(X86::FP4, MOTy::Def) - .addReg(X86::FP3, MOTy::Def) - .addReg(X86::FP2, MOTy::Def) - .addReg(X86::FP1, MOTy::Def) - .addReg(X86::FP0, MOTy::Def); - - mbb.insert(mii.base(), instr); - - for (unsigned i = 0; i < instr->getNumOperands(); ++i) { - LV.HandlePhysRegDef(instr->getOperand(i).getAllocatedRegNum(), instr); - - // force live variables to compute that these registers are dead - LV.HandlePhysRegDef(instr->getOperand(i).getAllocatedRegNum(), 0); - } - } - return true; -} diff --git a/lib/Target/X86/InstSelectSimple.cpp b/lib/Target/X86/InstSelectSimple.cpp index 4113076ad27..ca65c446ea7 100644 --- a/lib/Target/X86/InstSelectSimple.cpp +++ b/lib/Target/X86/InstSelectSimple.cpp @@ -834,6 +834,7 @@ void ISel::promote32(unsigned targetReg, const ValueRecord &VR) { /// ret float/double : Top of FP stack /// void ISel::visitReturnInst(ReturnInst &I) { + BuildMI(BB, X86::FP_REG_KILL, 0); if (I.getNumOperands() == 0) { BuildMI(BB, X86::RET, 0); // Just emit a 'ret' instruction return; @@ -882,6 +883,7 @@ static inline BasicBlock *getBlockAfter(BasicBlock *BB) { /// void ISel::visitBranchInst(BranchInst &BI) { BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one + BuildMI(BB, X86::FP_REG_KILL, 0); if (!BI.isConditional()) { // Unconditional branch? if (BI.getSuccessor(0) != NextBB) diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp index c3f1461db30..13e9d762f5d 100644 --- a/lib/Target/X86/X86CodeEmitter.cpp +++ b/lib/Target/X86/X86CodeEmitter.cpp @@ -493,7 +493,9 @@ void Emitter::emitInstruction(MachineInstr &MI) { switch (Desc.TSFlags & X86II::FormMask) { default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!"); case X86II::Pseudo: - if (Opcode != X86::IMPLICIT_USE && Opcode != X86::IMPLICIT_DEF) + if (Opcode != X86::IMPLICIT_USE && + Opcode != X86::IMPLICIT_DEF && + Opcode != X86::FP_REG_KILL) std::cerr << "X86 Machine Code Emitter: No 'form', not emitting: " << MI; break; diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp index b8934769965..8673fd61cdb 100644 --- a/lib/Target/X86/X86FloatingPoint.cpp +++ b/lib/Target/X86/X86FloatingPoint.cpp @@ -603,55 +603,3 @@ void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) { I = MBB->erase(I)-1; // Remove the pseudo instruction delete MI; } - -namespace { - struct FPK : public MachineFunctionPass { - virtual const char *getPassName() const { return "X86 FP Killer"; } - virtual bool runOnMachineFunction(MachineFunction &MF); - virtual void getAnalysisUsage(AnalysisUsage &AU) const { - AU.addPreserved(); - AU.addRequired(); - AU.addPreservedID(PHIEliminationID); - AU.addRequiredID(PHIEliminationID); - MachineFunctionPass::getAnalysisUsage(AU); - } - }; -} - -FunctionPass *llvm::createX86FloatingPointKillerPass() { return new FPK(); } - -bool FPK::runOnMachineFunction(MachineFunction &MF) { - const TargetInstrInfo& tii = MF.getTarget().getInstrInfo();; - LiveVariables &LV = getAnalysis(); - - for (MachineFunction::iterator - mbbi = MF.begin(), mbbe = MF.end(); mbbi != mbbe; ++mbbi) { - MachineBasicBlock& mbb = *mbbi; - MachineBasicBlock::reverse_iterator mii = mbb.rbegin(); - // rewind to the last non terminating instruction - while (mii != mbb.rend() && tii.isTerminatorInstr((*mii)->getOpcode())) - ++mii; - - // add implicit def for all virtual floating point registers so that - // they are spilled at the end of each basic block, since our - // register stackifier doesn't handle them otherwise. - MachineInstr* instr = BuildMI(X86::IMPLICIT_DEF, 7) - .addReg(X86::FP6, MOTy::Def) - .addReg(X86::FP5, MOTy::Def) - .addReg(X86::FP4, MOTy::Def) - .addReg(X86::FP3, MOTy::Def) - .addReg(X86::FP2, MOTy::Def) - .addReg(X86::FP1, MOTy::Def) - .addReg(X86::FP0, MOTy::Def); - - mbb.insert(mii.base(), instr); - - for (unsigned i = 0; i < instr->getNumOperands(); ++i) { - LV.HandlePhysRegDef(instr->getOperand(i).getAllocatedRegNum(), instr); - - // force live variables to compute that these registers are dead - LV.HandlePhysRegDef(instr->getOperand(i).getAllocatedRegNum(), 0); - } - } - return true; -} diff --git a/lib/Target/X86/X86ISelSimple.cpp b/lib/Target/X86/X86ISelSimple.cpp index 4113076ad27..ca65c446ea7 100644 --- a/lib/Target/X86/X86ISelSimple.cpp +++ b/lib/Target/X86/X86ISelSimple.cpp @@ -834,6 +834,7 @@ void ISel::promote32(unsigned targetReg, const ValueRecord &VR) { /// ret float/double : Top of FP stack /// void ISel::visitReturnInst(ReturnInst &I) { + BuildMI(BB, X86::FP_REG_KILL, 0); if (I.getNumOperands() == 0) { BuildMI(BB, X86::RET, 0); // Just emit a 'ret' instruction return; @@ -882,6 +883,7 @@ static inline BasicBlock *getBlockAfter(BasicBlock *BB) { /// void ISel::visitBranchInst(BranchInst &BI) { BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one + BuildMI(BB, X86::FP_REG_KILL, 0); if (!BI.isConditional()) { // Unconditional branch? if (BI.getSuccessor(0) != NextBB) diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index eecc5453479..6cd514bad87 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -115,7 +115,9 @@ def ADJCALLSTACKDOWN : X86Inst<"ADJCALLSTACKDOWN", 0, Pseudo, NoArg>; def ADJCALLSTACKUP : X86Inst<"ADJCALLSTACKUP", 0, Pseudo, NoArg>; def IMPLICIT_USE : X86Inst<"IMPLICIT_USE", 0, Pseudo, NoArg>; def IMPLICIT_DEF : X86Inst<"IMPLICIT_DEF", 0, Pseudo, NoArg>; - +let isTerminator = 1 in + let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in + def FP_REG_KILL : X86Inst<"FP_REG_KILL", 0, Pseudo, NoArg>; //===----------------------------------------------------------------------===// // Control Flow Instructions... // diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp index a56e35f4d6f..8440838fbfa 100644 --- a/lib/Target/X86/X86TargetMachine.cpp +++ b/lib/Target/X86/X86TargetMachine.cpp @@ -76,11 +76,6 @@ bool X86TargetMachine::addPassesToEmitAssembly(PassManager &PM, if (PrintCode) PM.add(createMachineFunctionPrinterPass()); - // kill floating point registers at the end of basic blocks. this is - // done because the floating point register stackifier cannot handle - // floating point regs that are live across basic blocks. - //PM.add(createX86FloatingPointKillerPass()); - // Perform register allocation to convert to a concrete x86 representation PM.add(createRegisterAllocator()); @@ -138,11 +133,6 @@ void X86JITInfo::addPassesToJITCompile(FunctionPassManager &PM) { if (PrintCode) PM.add(createMachineFunctionPrinterPass()); - // kill floating point registers at the end of basic blocks. this is - // done because the floating point register stackifier cannot handle - // floating point regs that are live across basic blocks. - //PM.add(createX86FloatingPointKillerPass()); - // Perform register allocation to convert to a concrete x86 representation PM.add(createRegisterAllocator());