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[SystemZ] Add floating-point load-and-test instructions

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These instructions can also be used as comparisons with zero.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187882 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Sandiford 2013-08-07 11:03:34 +00:00
parent c11b107f21
commit e0bbf7288c
9 changed files with 139 additions and 0 deletions
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11
lib/Target/SystemZ/SystemZInstrFP.td
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@ -39,6 +39,17 @@ let neverHasSideEffects = 1 in {
def LXR : UnaryRRE<"lx", 0xB365, null_frag, FP128, FP128>;
}
// Moves between two floating-point registers that also set the condition
// codes.
let Defs = [CC] in {
defm LTEBR : LoadAndTestRRE<"lteb", 0xB302, FP32>;
defm LTDBR : LoadAndTestRRE<"ltdb", 0xB312, FP64>;
defm LTXBR : LoadAndTestRRE<"ltxb", 0xB342, FP128>;
}
def : CompareZeroFP<LTEBRCompare, FP32>;
def : CompareZeroFP<LTDBRCompare, FP64>;
def : CompareZeroFP<LTXBRCompare, FP128>;
// Moves between 64-bit integer and floating-point registers.
def LGDR : UnaryRRE<"lgd", 0xB3CD, bitconvert, GR64, FP64>;
def LDGR : UnaryRRE<"ldg", 0xB3C1, bitconvert, FP64, GR64>;

9
lib/Target/SystemZ/SystemZInstrFormats.td
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@ -1289,6 +1289,15 @@ class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
let DisableEncoding = "$R1src";
}
// A floating-point load-and test operation. Create both a normal unary
// operation and one that acts as a comparison against zero.
multiclass LoadAndTestRRE<string mnemonic, bits<16> opcode,
RegisterOperand cls> {
def "" : UnaryRRE<mnemonic, opcode, null_frag, cls, cls>;
let isCodeGenOnly = 1 in
def Compare : CompareRRE<mnemonic, opcode, null_frag, cls, cls>;
}
//===----------------------------------------------------------------------===//
// Pseudo instructions
//===----------------------------------------------------------------------===//

6
lib/Target/SystemZ/SystemZPatterns.td
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@ -79,3 +79,9 @@ multiclass MVCLoadStore<SDPatternOperator load, SDPatternOperator store,
bdaddr12only:$src),
(insn bdaddr12only:$dest, bdaddr12only:$src, length)>;
}
// Record that INSN is a LOAD AND TEST that can be used to compare
// registers in CLS against zero. The instruction has separate R1 and R2
// operands, but they must be the same when the instruction is used like this.
class CompareZeroFP<Instruction insn, RegisterOperand cls>
: Pat<(z_cmp cls:$reg, (fpimm0)), (insn cls:$reg, cls:$reg)>;

12
test/CodeGen/SystemZ/fp-cmp-01.ll
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@ -147,3 +147,15 @@ define float @f7(float *%ptr0) {
ret float %sel10
}
; Check comparison with zero.
define i64 @f8(i64 %a, i64 %b, float %f) {
; CHECK-LABEL: f8:
; CHECK: ltebr %f0, %f0
; CHECK-NEXT: je
; CHECK: lgr %r2, %r3
; CHECK: br %r14
%cond = fcmp oeq float %f, 0.0
%res = select i1 %cond, i64 %a, i64 %b
ret i64 %res
}

12
test/CodeGen/SystemZ/fp-cmp-02.ll
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@ -147,3 +147,15 @@ define double @f7(double *%ptr0) {
ret double %sel10
}
; Check comparison with zero.
define i64 @f8(i64 %a, i64 %b, double %f) {
; CHECK-LABEL: f8:
; CHECK: ltdbr %f0, %f0
; CHECK-NEXT: je
; CHECK: lgr %r2, %r3
; CHECK: br %r14
%cond = fcmp oeq double %f, 0.0
%res = select i1 %cond, i64 %a, i64 %b
ret i64 %res
}

15
test/CodeGen/SystemZ/fp-cmp-03.ll
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@ -18,3 +18,18 @@ define i64 @f1(i64 %a, i64 %b, fp128 *%ptr, float %f2) {
%res = select i1 %cond, i64 %a, i64 %b
ret i64 %res
}
; Check comparison with zero.
define i64 @f2(i64 %a, i64 %b, fp128 *%ptr) {
; CHECK-LABEL: f2:
; CHECK: ld %f0, 0(%r4)
; CHECK: ld %f2, 8(%r4)
; CHECK: ltxbr %f0, %f0
; CHECK-NEXT: je
; CHECK: lgr %r2, %r3
; CHECK: br %r14
%f = load fp128 *%ptr
%cond = fcmp oeq fp128 %f, 0xL00000000000000000000000000000000
%res = select i1 %cond, i64 %a, i64 %b
ret i64 %res
}

36
test/MC/Disassembler/SystemZ/insns.txt
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@ -3643,6 +3643,30 @@
# CHECK: lt %r15, 0
0xe3 0xf0 0x00 0x00 0x00 0x12
# CHECK: ltdbr %f0, %f9
0xb3 0x12 0x00 0x09
# CHECK: ltdbr %f0, %f15
0xb3 0x12 0x00 0x0f
# CHECK: ltdbr %f15, %f0
0xb3 0x12 0x00 0xf0
# CHECK: ltdbr %f15, %f9
0xb3 0x12 0x00 0xf9
# CHECK: ltebr %f0, %f9
0xb3 0x02 0x00 0x09
# CHECK: ltebr %f0, %f15
0xb3 0x02 0x00 0x0f
# CHECK: ltebr %f15, %f0
0xb3 0x02 0x00 0xf0
# CHECK: ltebr %f15, %f9
0xb3 0x02 0x00 0xf9
# CHECK: ltg %r0, -524288
0xe3 0x00 0x00 0x00 0x80 0x02
@ -3739,6 +3763,18 @@
# CHECK: ltr %r15, %r9
0x12 0xf9
# CHECK: ltxbr %f0, %f9
0xb3 0x42 0x00 0x09
# CHECK: ltxbr %f0, %f13
0xb3 0x42 0x00 0x0d
# CHECK: ltxbr %f13, %f0
0xb3 0x42 0x00 0xd0
# CHECK: ltxbr %f13, %f9
0xb3 0x42 0x00 0xd9
# CHECK: lxr %f0, %f8
0xb3 0x65 0x00 0x08

8
test/MC/SystemZ/insn-bad.s
View File

@ -1644,6 +1644,14 @@
ltgf %r0, -524289
ltgf %r0, 524288
#CHECK: error: invalid register pair
#CHECK: ltxbr %f0, %f14
#CHECK: error: invalid register pair
#CHECK: ltxbr %f14, %f0
ltxbr %f0, %f14
ltxbr %f14, %f0
#CHECK: error: invalid register pair
#CHECK: lxr %f0, %f2
#CHECK: error: invalid register pair

30
test/MC/SystemZ/insn-good.s
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@ -4904,6 +4904,26 @@
ltgf %r0, 524287(%r15,%r1)
ltgf %r15, 0
#CHECK: ltdbr %f0, %f9 # encoding: [0xb3,0x12,0x00,0x09]
#CHECK: ltdbr %f0, %f15 # encoding: [0xb3,0x12,0x00,0x0f]
#CHECK: ltdbr %f15, %f0 # encoding: [0xb3,0x12,0x00,0xf0]
#CHECK: ltdbr %f15, %f9 # encoding: [0xb3,0x12,0x00,0xf9]
ltdbr %f0,%f9
ltdbr %f0,%f15
ltdbr %f15,%f0
ltdbr %f15,%f9
#CHECK: ltebr %f0, %f9 # encoding: [0xb3,0x02,0x00,0x09]
#CHECK: ltebr %f0, %f15 # encoding: [0xb3,0x02,0x00,0x0f]
#CHECK: ltebr %f15, %f0 # encoding: [0xb3,0x02,0x00,0xf0]
#CHECK: ltebr %f15, %f9 # encoding: [0xb3,0x02,0x00,0xf9]
ltebr %f0,%f9
ltebr %f0,%f15
ltebr %f15,%f0
ltebr %f15,%f9
#CHECK: ltgfr %r0, %r9 # encoding: [0xb9,0x12,0x00,0x09]
#CHECK: ltgfr %r0, %r15 # encoding: [0xb9,0x12,0x00,0x0f]
#CHECK: ltgfr %r15, %r0 # encoding: [0xb9,0x12,0x00,0xf0]
@ -4934,6 +4954,16 @@
ltr %r15,%r0
ltr %r15,%r9
#CHECK: ltxbr %f0, %f9 # encoding: [0xb3,0x42,0x00,0x09]
#CHECK: ltxbr %f0, %f13 # encoding: [0xb3,0x42,0x00,0x0d]
#CHECK: ltxbr %f13, %f0 # encoding: [0xb3,0x42,0x00,0xd0]
#CHECK: ltxbr %f13, %f9 # encoding: [0xb3,0x42,0x00,0xd9]
ltxbr %f0,%f9
ltxbr %f0,%f13
ltxbr %f13,%f0
ltxbr %f13,%f9
#CHECK: lxr %f0, %f8 # encoding: [0xb3,0x65,0x00,0x08]
#CHECK: lxr %f0, %f13 # encoding: [0xb3,0x65,0x00,0x0d]
#CHECK: lxr %f13, %f0 # encoding: [0xb3,0x65,0x00,0xd0]