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[SystemZ] Add floating-point load-and-test instructions
These instructions can also be used as comparisons with zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187882 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -39,6 +39,17 @@ let neverHasSideEffects = 1 in {
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def LXR : UnaryRRE<"lx", 0xB365, null_frag, FP128, FP128>;
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}
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// Moves between two floating-point registers that also set the condition
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// codes.
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let Defs = [CC] in {
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defm LTEBR : LoadAndTestRRE<"lteb", 0xB302, FP32>;
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defm LTDBR : LoadAndTestRRE<"ltdb", 0xB312, FP64>;
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defm LTXBR : LoadAndTestRRE<"ltxb", 0xB342, FP128>;
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}
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def : CompareZeroFP<LTEBRCompare, FP32>;
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def : CompareZeroFP<LTDBRCompare, FP64>;
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def : CompareZeroFP<LTXBRCompare, FP128>;
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// Moves between 64-bit integer and floating-point registers.
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def LGDR : UnaryRRE<"lgd", 0xB3CD, bitconvert, GR64, FP64>;
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def LDGR : UnaryRRE<"ldg", 0xB3C1, bitconvert, FP64, GR64>;
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@ -1289,6 +1289,15 @@ class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
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let DisableEncoding = "$R1src";
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}
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// A floating-point load-and test operation. Create both a normal unary
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// operation and one that acts as a comparison against zero.
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multiclass LoadAndTestRRE<string mnemonic, bits<16> opcode,
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RegisterOperand cls> {
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def "" : UnaryRRE<mnemonic, opcode, null_frag, cls, cls>;
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let isCodeGenOnly = 1 in
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def Compare : CompareRRE<mnemonic, opcode, null_frag, cls, cls>;
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}
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//===----------------------------------------------------------------------===//
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// Pseudo instructions
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//===----------------------------------------------------------------------===//
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@ -79,3 +79,9 @@ multiclass MVCLoadStore<SDPatternOperator load, SDPatternOperator store,
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bdaddr12only:$src),
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(insn bdaddr12only:$dest, bdaddr12only:$src, length)>;
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}
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// Record that INSN is a LOAD AND TEST that can be used to compare
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// registers in CLS against zero. The instruction has separate R1 and R2
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// operands, but they must be the same when the instruction is used like this.
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class CompareZeroFP<Instruction insn, RegisterOperand cls>
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: Pat<(z_cmp cls:$reg, (fpimm0)), (insn cls:$reg, cls:$reg)>;
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@ -147,3 +147,15 @@ define float @f7(float *%ptr0) {
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ret float %sel10
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}
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; Check comparison with zero.
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define i64 @f8(i64 %a, i64 %b, float %f) {
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; CHECK-LABEL: f8:
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; CHECK: ltebr %f0, %f0
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; CHECK-NEXT: je
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; CHECK: lgr %r2, %r3
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; CHECK: br %r14
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%cond = fcmp oeq float %f, 0.0
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%res = select i1 %cond, i64 %a, i64 %b
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ret i64 %res
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}
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@ -147,3 +147,15 @@ define double @f7(double *%ptr0) {
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ret double %sel10
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}
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; Check comparison with zero.
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define i64 @f8(i64 %a, i64 %b, double %f) {
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; CHECK-LABEL: f8:
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; CHECK: ltdbr %f0, %f0
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; CHECK-NEXT: je
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; CHECK: lgr %r2, %r3
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; CHECK: br %r14
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%cond = fcmp oeq double %f, 0.0
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%res = select i1 %cond, i64 %a, i64 %b
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ret i64 %res
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}
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@ -18,3 +18,18 @@ define i64 @f1(i64 %a, i64 %b, fp128 *%ptr, float %f2) {
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%res = select i1 %cond, i64 %a, i64 %b
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ret i64 %res
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}
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; Check comparison with zero.
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define i64 @f2(i64 %a, i64 %b, fp128 *%ptr) {
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; CHECK-LABEL: f2:
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; CHECK: ld %f0, 0(%r4)
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; CHECK: ld %f2, 8(%r4)
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; CHECK: ltxbr %f0, %f0
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; CHECK-NEXT: je
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; CHECK: lgr %r2, %r3
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; CHECK: br %r14
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%f = load fp128 *%ptr
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%cond = fcmp oeq fp128 %f, 0xL00000000000000000000000000000000
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%res = select i1 %cond, i64 %a, i64 %b
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ret i64 %res
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}
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@ -3643,6 +3643,30 @@
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# CHECK: lt %r15, 0
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0xe3 0xf0 0x00 0x00 0x00 0x12
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# CHECK: ltdbr %f0, %f9
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0xb3 0x12 0x00 0x09
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# CHECK: ltdbr %f0, %f15
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0xb3 0x12 0x00 0x0f
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# CHECK: ltdbr %f15, %f0
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0xb3 0x12 0x00 0xf0
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# CHECK: ltdbr %f15, %f9
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0xb3 0x12 0x00 0xf9
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# CHECK: ltebr %f0, %f9
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0xb3 0x02 0x00 0x09
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# CHECK: ltebr %f0, %f15
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0xb3 0x02 0x00 0x0f
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# CHECK: ltebr %f15, %f0
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0xb3 0x02 0x00 0xf0
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# CHECK: ltebr %f15, %f9
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0xb3 0x02 0x00 0xf9
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# CHECK: ltg %r0, -524288
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0xe3 0x00 0x00 0x00 0x80 0x02
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@ -3739,6 +3763,18 @@
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# CHECK: ltr %r15, %r9
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0x12 0xf9
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# CHECK: ltxbr %f0, %f9
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0xb3 0x42 0x00 0x09
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# CHECK: ltxbr %f0, %f13
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0xb3 0x42 0x00 0x0d
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# CHECK: ltxbr %f13, %f0
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0xb3 0x42 0x00 0xd0
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# CHECK: ltxbr %f13, %f9
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0xb3 0x42 0x00 0xd9
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# CHECK: lxr %f0, %f8
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0xb3 0x65 0x00 0x08
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@ -1644,6 +1644,14 @@
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ltgf %r0, -524289
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ltgf %r0, 524288
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#CHECK: error: invalid register pair
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#CHECK: ltxbr %f0, %f14
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#CHECK: error: invalid register pair
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#CHECK: ltxbr %f14, %f0
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ltxbr %f0, %f14
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ltxbr %f14, %f0
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#CHECK: error: invalid register pair
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#CHECK: lxr %f0, %f2
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#CHECK: error: invalid register pair
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@ -4904,6 +4904,26 @@
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ltgf %r0, 524287(%r15,%r1)
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ltgf %r15, 0
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#CHECK: ltdbr %f0, %f9 # encoding: [0xb3,0x12,0x00,0x09]
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#CHECK: ltdbr %f0, %f15 # encoding: [0xb3,0x12,0x00,0x0f]
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#CHECK: ltdbr %f15, %f0 # encoding: [0xb3,0x12,0x00,0xf0]
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#CHECK: ltdbr %f15, %f9 # encoding: [0xb3,0x12,0x00,0xf9]
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ltdbr %f0,%f9
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ltdbr %f0,%f15
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ltdbr %f15,%f0
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ltdbr %f15,%f9
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#CHECK: ltebr %f0, %f9 # encoding: [0xb3,0x02,0x00,0x09]
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#CHECK: ltebr %f0, %f15 # encoding: [0xb3,0x02,0x00,0x0f]
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#CHECK: ltebr %f15, %f0 # encoding: [0xb3,0x02,0x00,0xf0]
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#CHECK: ltebr %f15, %f9 # encoding: [0xb3,0x02,0x00,0xf9]
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ltebr %f0,%f9
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ltebr %f0,%f15
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ltebr %f15,%f0
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ltebr %f15,%f9
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#CHECK: ltgfr %r0, %r9 # encoding: [0xb9,0x12,0x00,0x09]
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#CHECK: ltgfr %r0, %r15 # encoding: [0xb9,0x12,0x00,0x0f]
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#CHECK: ltgfr %r15, %r0 # encoding: [0xb9,0x12,0x00,0xf0]
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@ -4934,6 +4954,16 @@
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ltr %r15,%r0
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ltr %r15,%r9
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#CHECK: ltxbr %f0, %f9 # encoding: [0xb3,0x42,0x00,0x09]
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#CHECK: ltxbr %f0, %f13 # encoding: [0xb3,0x42,0x00,0x0d]
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#CHECK: ltxbr %f13, %f0 # encoding: [0xb3,0x42,0x00,0xd0]
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#CHECK: ltxbr %f13, %f9 # encoding: [0xb3,0x42,0x00,0xd9]
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ltxbr %f0,%f9
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ltxbr %f0,%f13
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ltxbr %f13,%f0
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ltxbr %f13,%f9
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#CHECK: lxr %f0, %f8 # encoding: [0xb3,0x65,0x00,0x08]
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#CHECK: lxr %f0, %f13 # encoding: [0xb3,0x65,0x00,0x0d]
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#CHECK: lxr %f13, %f0 # encoding: [0xb3,0x65,0x00,0xd0]
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