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Had expand logic backward.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25105 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Laskey 2006-01-05 01:47:43 +00:00
parent abf6d1784b
commit e0bce71c42
7 changed files with 14 additions and 1 deletions
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2
lib/Target/Alpha/AlphaISelLowering.cpp
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@ -103,6 +103,8 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
// We want to legalize GlobalAddress and ConstantPool and
// ExternalSymbols nodes into the appropriate instructions to

2
lib/Target/IA64/IA64ISelLowering.cpp
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@ -74,6 +74,8 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
//IA64 has these, but they are not implemented
setOperationAction(ISD::CTTZ , MVT::i64 , Expand);

2
lib/Target/IA64/IA64ISelPattern.cpp
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@ -102,6 +102,8 @@ namespace {
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
computeRegisterProperties();

3
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -96,8 +96,9 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
// Support label based line numbers.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
// FIXME - use subtarget debug flags
if (TM.getSubtarget<PPCSubtarget>().isDarwin())
if (!TM.getSubtarget<PPCSubtarget>().isDarwin())
setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
// We want to legalize GlobalAddress and ConstantPool nodes into the

2
lib/Target/Sparc/SparcISelDAGToDAG.cpp
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@ -153,6 +153,8 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
computeRegisterProperties();
}

2
lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
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@ -153,6 +153,8 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
computeRegisterProperties();
}

2
lib/Target/X86/X86ISelLowering.cpp
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@ -130,6 +130,8 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
if (X86ScalarSSE) {
// Set up the FP register classes.