From e0c2b6b9a8ac874c7b57e445ff1513f0e37581f4 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Thu, 1 Feb 2007 03:04:49 +0000 Subject: [PATCH] .set pc relative displacement bug: label should be moved down one instruction to just before the add r1, pc: Before: .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4)) LPCRELL0: mov r1, #PCRELV0 add r1, pc Now: .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4)) mov r1, #PCRELV0 LPCRELL0: add r1, pc git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33744 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrThumb.td | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index 416d4305037..b0e531cdc84 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -480,17 +480,17 @@ let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler. // assembler. def tLEApcrel : TIx2<(ops GPR:$dst, i32imm:$label), !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(", - "${:private}PCRELL${:uid}+4))\n"), - !strconcat("${:private}PCRELL${:uid}:\n\t", - "mov $dst, #PCRELV${:uid}\n\tadd $dst, pc")), + "${:private}PCRELL${:uid}+6))\n"), + !strconcat("\tmov $dst, #PCRELV${:uid}\n", + "${:private}PCRELL${:uid}:\n\tadd $dst, pc")), []>; def tLEApcrelJT : TIx2<(ops GPR:$dst, i32imm:$label, i32imm:$id), !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(", "${:private}PCRELL${:uid}+4))\n"), - !strconcat("${:private}PCRELL${:uid}:\n\t", - "mov $dst, #PCRELV${:uid}\n\tadd $dst, pc")), - []>; + !strconcat("\tmov $dst, #PCRELV${:uid}\n", + "${:private}PCRELL${:uid}:\n\tadd $dst, pc")), + []>; //===----------------------------------------------------------------------===// // Non-Instruction Patterns