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[SparcV9]: Expand MULHU/MULHS:i64 and UMUL_LOHI/SMUL_LOHI:i64 on sparcv9.

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This fixes PR18150.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196735 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Venkatraman Govindaraju 2013-12-08 22:06:07 +00:00
parent 8186046028
commit e0dc442801
2 changed files with 23 additions and 0 deletions
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7
lib/Target/Sparc/SparcISelLowering.cpp
View File

@ -1462,6 +1462,13 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
if (Subtarget->is64Bit()) {
setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
setOperationAction(ISD::MULHU, MVT::i64, Expand);
setOperationAction(ISD::MULHS, MVT::i64, Expand);
}
// VASTART needs to be custom lowered to use the VarArgsFrameIndex.
setOperationAction(ISD::VASTART , MVT::Other, Custom);
// VAARG needs to be lowered to not do unaligned accesses for doubles.

16
test/CodeGen/SPARC/rem.ll
View File

@ -21,3 +21,19 @@ define i64 @test2(i64 %X, i64 %Y) {
%tmp1 = urem i64 %X, %Y
ret i64 %tmp1
}
; PR18150
; CHECK-LABEL: test3
; CHECK: sethi 2545, [[R0:%[gilo][0-7]]]
; CHECK: or [[R0]], 379, [[R1:%[gilo][0-7]]]
; CHECK: mulx %o0, [[R1]], [[R2:%[gilo][0-7]]]
; CHECK: udivx [[R2]], 1021, [[R3:%[gilo][0-7]]]
; CHECK: mulx [[R3]], 1021, [[R4:%[gilo][0-7]]]
; CHECK: sub [[R2]], [[R4]], %o0
define i64 @test3(i64 %b) {
entry:
%mul = mul i64 %b, 2606459
%rem = urem i64 %mul, 1021
ret i64 %rem
}