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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77231 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-07-27 18:48:45 +00:00
parent 78703ddafe
commit e0f21bd47f
4 changed files with 1 additions and 17 deletions
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6
lib/Target/ARM/ARMBaseInstrInfo.h
View File

@ -163,12 +163,8 @@ namespace ARMII {
/// ///
enum Op { enum Op {
ADDri, ADDri,
ADDrs,
ADDrr,
MOVr, MOVr,
SUBri, SUBri
SUBrs,
SUBrr
}; };
} }

4
lib/Target/ARM/ARMInstrInfo.cpp
View File

@ -66,12 +66,8 @@ unsigned ARMInstrInfo::
getOpcode(ARMII::Op Op) const { getOpcode(ARMII::Op Op) const {
switch (Op) { switch (Op) {
case ARMII::ADDri: return ARM::ADDri; case ARMII::ADDri: return ARM::ADDri;
case ARMII::ADDrs: return ARM::ADDrs;
case ARMII::ADDrr: return ARM::ADDrr;
case ARMII::MOVr: return ARM::MOVr; case ARMII::MOVr: return ARM::MOVr;
case ARMII::SUBri: return ARM::SUBri; case ARMII::SUBri: return ARM::SUBri;
case ARMII::SUBrs: return ARM::SUBrs;
case ARMII::SUBrr: return ARM::SUBrr;
default: default:
break; break;
} }

4
lib/Target/ARM/Thumb1InstrInfo.cpp
View File

@ -33,12 +33,8 @@ unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
unsigned Thumb1InstrInfo::getOpcode(ARMII::Op Op) const { unsigned Thumb1InstrInfo::getOpcode(ARMII::Op Op) const {
switch (Op) { switch (Op) {
case ARMII::ADDri: return ARM::tADDi8; case ARMII::ADDri: return ARM::tADDi8;
case ARMII::ADDrs: return 0;
case ARMII::ADDrr: return ARM::tADDrr;
case ARMII::MOVr: return ARM::tMOVr; case ARMII::MOVr: return ARM::tMOVr;
case ARMII::SUBri: return ARM::tSUBi8; case ARMII::SUBri: return ARM::tSUBi8;
case ARMII::SUBrs: return 0;
case ARMII::SUBrr: return ARM::tSUBrr;
default: default:
break; break;
} }

4
lib/Target/ARM/Thumb2InstrInfo.cpp
View File

@ -34,12 +34,8 @@ unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
unsigned Thumb2InstrInfo::getOpcode(ARMII::Op Op) const { unsigned Thumb2InstrInfo::getOpcode(ARMII::Op Op) const {
switch (Op) { switch (Op) {
case ARMII::ADDri: return ARM::t2ADDri; case ARMII::ADDri: return ARM::t2ADDri;
case ARMII::ADDrs: return ARM::t2ADDrs;
case ARMII::ADDrr: return ARM::t2ADDrr;
case ARMII::MOVr: return ARM::t2MOVr; case ARMII::MOVr: return ARM::t2MOVr;
case ARMII::SUBri: return ARM::t2SUBri; case ARMII::SUBri: return ARM::t2SUBri;
case ARMII::SUBrs: return ARM::t2SUBrs;
case ARMII::SUBrr: return ARM::t2SUBrr;
default: default:
break; break;
} }