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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-18 12:29:21 +00:00
Added option -disable-x86-shuffle-opti to disable X86 specific vector shuffle optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30723 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -31,12 +31,14 @@
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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// FIXME: temporary.
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#include "llvm/Support/CommandLine.h"
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static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden,
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cl::desc("Enable fastcc on X86"));
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static cl::opt<bool> NoShuffleOpti("disable-x86-shuffle-opti", cl::Hidden,
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cl::desc("Disable vector shuffle optimizations on X86"));
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X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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: TargetLowering(TM) {
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@ -3348,7 +3350,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
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return SDOperand();
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// Special case for single non-zero element.
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if (NumNonZero == 1) {
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if (!NoShuffleOpti && NumNonZero == 1) {
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unsigned Idx = CountTrailingZeros_32(NonZeros);
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SDOperand Item = Op.getOperand(Idx);
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Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
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@ -3373,7 +3375,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
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}
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}
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// Let legalizer expand 2-widde build_vector's.
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// Let legalizer expand 2-wide build_vector's.
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if (EVTBits == 64)
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return SDOperand();
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@ -3487,68 +3489,71 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
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if (isSplatMask(PermMask.Val)) {
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if (NumElems <= 4) return Op;
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// Promote it to a v4i32 splat.
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return PromoteSplat(Op, DAG);
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if (!NoShuffleOpti)
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return PromoteSplat(Op, DAG);
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}
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if (X86::isMOVLMask(PermMask.Val))
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return (V1IsUndef) ? V2 : Op;
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if (!NoShuffleOpti) {
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if (X86::isMOVLMask(PermMask.Val))
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return (V1IsUndef) ? V2 : Op;
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if (X86::isMOVSHDUPMask(PermMask.Val) ||
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X86::isMOVSLDUPMask(PermMask.Val) ||
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X86::isMOVHLPSMask(PermMask.Val) ||
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X86::isMOVHPMask(PermMask.Val) ||
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X86::isMOVLPMask(PermMask.Val))
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return Op;
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if (X86::isMOVSHDUPMask(PermMask.Val) ||
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X86::isMOVSLDUPMask(PermMask.Val) ||
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X86::isMOVHLPSMask(PermMask.Val) ||
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X86::isMOVHPMask(PermMask.Val) ||
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X86::isMOVLPMask(PermMask.Val))
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return Op;
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if (ShouldXformToMOVHLPS(PermMask.Val) ||
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ShouldXformToMOVLP(V1.Val, PermMask.Val))
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return CommuteVectorShuffle(Op, DAG);
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if (ShouldXformToMOVHLPS(PermMask.Val) ||
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ShouldXformToMOVLP(V1.Val, PermMask.Val))
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return CommuteVectorShuffle(Op, DAG);
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bool V1IsSplat = isSplatVector(V1.Val);
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bool V2IsSplat = isSplatVector(V2.Val);
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if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
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Op = CommuteVectorShuffle(Op, DAG);
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V1 = Op.getOperand(0);
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V2 = Op.getOperand(1);
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PermMask = Op.getOperand(2);
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std::swap(V1IsSplat, V2IsSplat);
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std::swap(V1IsUndef, V2IsUndef);
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}
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if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) {
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if (V2IsUndef) return V1;
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Op = CommuteVectorShuffle(Op, DAG);
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V1 = Op.getOperand(0);
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V2 = Op.getOperand(1);
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PermMask = Op.getOperand(2);
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if (V2IsSplat) {
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// V2 is a splat, so the mask may be malformed. That is, it may point
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// to any V2 element. The instruction selectior won't like this. Get
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// a corrected mask and commute to form a proper MOVS{S|D}.
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SDOperand NewMask = getMOVLMask(NumElems, DAG);
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if (NewMask.Val != PermMask.Val)
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Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
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bool V1IsSplat = isSplatVector(V1.Val);
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bool V2IsSplat = isSplatVector(V2.Val);
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if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
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Op = CommuteVectorShuffle(Op, DAG);
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V1 = Op.getOperand(0);
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V2 = Op.getOperand(1);
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PermMask = Op.getOperand(2);
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std::swap(V1IsSplat, V2IsSplat);
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std::swap(V1IsUndef, V2IsUndef);
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}
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return Op;
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}
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if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
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X86::isUNPCKLMask(PermMask.Val) ||
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X86::isUNPCKHMask(PermMask.Val))
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return Op;
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if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) {
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if (V2IsUndef) return V1;
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Op = CommuteVectorShuffle(Op, DAG);
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V1 = Op.getOperand(0);
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V2 = Op.getOperand(1);
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PermMask = Op.getOperand(2);
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if (V2IsSplat) {
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// V2 is a splat, so the mask may be malformed. That is, it may point
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// to any V2 element. The instruction selectior won't like this. Get
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// a corrected mask and commute to form a proper MOVS{S|D}.
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SDOperand NewMask = getMOVLMask(NumElems, DAG);
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if (NewMask.Val != PermMask.Val)
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Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
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}
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return Op;
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}
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if (V2IsSplat) {
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// Normalize mask so all entries that point to V2 points to its first
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// element then try to match unpck{h|l} again. If match, return a
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// new vector_shuffle with the corrected mask.
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SDOperand NewMask = NormalizeMask(PermMask, DAG);
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if (NewMask.Val != PermMask.Val) {
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if (X86::isUNPCKLMask(PermMask.Val, true)) {
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SDOperand NewMask = getUnpacklMask(NumElems, DAG);
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return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
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} else if (X86::isUNPCKHMask(PermMask.Val, true)) {
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SDOperand NewMask = getUnpackhMask(NumElems, DAG);
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return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
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if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
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X86::isUNPCKLMask(PermMask.Val) ||
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X86::isUNPCKHMask(PermMask.Val))
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return Op;
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if (V2IsSplat) {
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// Normalize mask so all entries that point to V2 points to its first
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// element then try to match unpck{h|l} again. If match, return a
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// new vector_shuffle with the corrected mask.
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SDOperand NewMask = NormalizeMask(PermMask, DAG);
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if (NewMask.Val != PermMask.Val) {
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if (X86::isUNPCKLMask(PermMask.Val, true)) {
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SDOperand NewMask = getUnpacklMask(NumElems, DAG);
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return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
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} else if (X86::isUNPCKHMask(PermMask.Val, true)) {
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SDOperand NewMask = getUnpackhMask(NumElems, DAG);
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return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
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}
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}
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}
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}
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