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Update register class references to use the global constant ARM::*RegisterClass names.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81556 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2009-09-11 19:49:06 +00:00
parent d00025a6c8
commit e11a8f565c
2 changed files with 30 additions and 26 deletions
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54
lib/Target/ARM/ARMBaseRegisterInfo.cpp
View File

@ -164,42 +164,46 @@ ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
const TargetRegisterClass* const * const TargetRegisterClass* const *
ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
static const TargetRegisterClass * const CalleeSavedRegClasses[] = { static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
&ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass,
&ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass,
&ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass,
&ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
&ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
ARM::DPRRegisterClass, ARM::DPRRegisterClass,
0 0
}; };
static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = { static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = {
&ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass,
&ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::tGPRRegisterClass,
&ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass, ARM::tGPRRegisterClass,ARM::tGPRRegisterClass,ARM::tGPRRegisterClass,
&ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
&ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
ARM::DPRRegisterClass, ARM::DPRRegisterClass,
0 0
}; };
static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = { static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = {
&ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass,
&ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass,
&ARM::GPRRegClass, &ARM::GPRRegClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass,
&ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
&ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
ARM::DPRRegisterClass, ARM::DPRRegisterClass,
0 0
}; };
static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={ static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={
&ARM::GPRRegClass, &ARM::tGPRRegClass, &ARM::tGPRRegClass, ARM::GPRRegisterClass, ARM::tGPRRegisterClass, ARM::tGPRRegisterClass,
&ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass, ARM::tGPRRegisterClass, ARM::tGPRRegisterClass, ARM::GPRRegisterClass,
&ARM::GPRRegClass, &ARM::GPRRegClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass,
&ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
&ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
ARM::DPRRegisterClass, ARM::DPRRegisterClass,
0 0
}; };
@ -245,7 +249,7 @@ bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
const TargetRegisterClass * const TargetRegisterClass *
ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const { ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
return &ARM::GPRRegClass; return ARM::GPRRegisterClass;
} }
/// getAllocationOrder - Returns the register allocation order for a specified /// getAllocationOrder - Returns the register allocation order for a specified
@ -536,7 +540,7 @@ ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
} }
} }
if (CSRegClasses[i] == &ARM::GPRRegClass) { if (CSRegClasses[i] == ARM::GPRRegisterClass) {
if (Spilled) { if (Spilled) {
NumGPRSpills++; NumGPRSpills++;
@ -680,7 +684,7 @@ ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
} }
} else { } else {
// Reserve a slot closest to SP or frame pointer. // Reserve a slot closest to SP or frame pointer.
const TargetRegisterClass *RC = &ARM::GPRRegClass; const TargetRegisterClass *RC = ARM::GPRRegisterClass;
RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
RC->getAlignment())); RC->getAlignment()));
} }
@ -1068,10 +1072,10 @@ ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
// If the offset we have is too large to fit into the instruction, we need // If the offset we have is too large to fit into the instruction, we need
// to form it with a series of ADDri's. Do this by taking 8-bit chunks // to form it with a series of ADDri's. Do this by taking 8-bit chunks
// out of 'Offset'. // out of 'Offset'.
unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI); unsigned ScratchReg = findScratchRegister(RS, ARM::GPRRegisterClass, AFI);
if (ScratchReg == 0) if (ScratchReg == 0)
// No register is "free". Scavenge a register. // No register is "free". Scavenge a register.
ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj); ScratchReg = RS->scavengeRegister(ARM::GPRRegisterClass, II, SPAdj);
int PIdx = MI.findFirstPredOperandIdx(); int PIdx = MI.findFirstPredOperandIdx();
ARMCC::CondCodes Pred = (PIdx == -1) ARMCC::CondCodes Pred = (PIdx == -1)
? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();

2
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
View File

@ -942,7 +942,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
// First advance to the instruction just before the start of the chain. // First advance to the instruction just before the start of the chain.
AdvanceRS(MBB, MemOps); AdvanceRS(MBB, MemOps);
// Find a scratch register. // Find a scratch register.
unsigned Scratch = RS->FindUnusedReg(&ARM::GPRRegClass); unsigned Scratch = RS->FindUnusedReg(ARM::GPRRegisterClass);
// Process the load / store instructions. // Process the load / store instructions.
RS->forward(prior(MBBI)); RS->forward(prior(MBBI));