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Implement initial prolog/epilog code insertion methods.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11979 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2004-02-29 05:18:30 +00:00
parent 7598a1a9a8
commit e1274de2c9
4 changed files with 34 additions and 12 deletions
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20
lib/Target/Sparc/SparcRegisterInfo.cpp
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@@ -13,7 +13,10 @@
#include "SparcV8.h" #include "SparcV8.h"
#include "SparcV8RegisterInfo.h" #include "SparcV8RegisterInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Type.h" #include "llvm/Type.h"
#include "Support/STLExtras.h"
using namespace llvm; using namespace llvm;
SparcV8RegisterInfo::SparcV8RegisterInfo() SparcV8RegisterInfo::SparcV8RegisterInfo()
@@ -60,18 +63,23 @@ SparcV8RegisterInfo::eliminateFrameIndex(MachineFunction &MF,
abort(); abort();
} }
void SparcV8RegisterInfo::processFunctionBeforeFrameFinalized( void SparcV8RegisterInfo::
MachineFunction &MF) const { processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
abort();
}
void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const { void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
abort(); MachineBasicBlock &MBB = MF.front();
// Eventually this should emit the correct save instruction based on the
// number of bytes in the frame. For now we just hardcode it.
BuildMI(MBB, MBB.begin(), V8::SAVEi, 2, V8::SP).addImm(-122).addReg(V8::SP);
} }
void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF, void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const { MachineBasicBlock &MBB) const {
abort(); MachineBasicBlock::iterator MBBI = prior(MBB.end());
assert(MBBI->getOpcode() == V8::JMPLi &&
"Can only put epilog before return instruction!");
BuildMI(MBB, MBBI, V8::RESTOREi, 2, V8::O0).addImm(0).addReg(V8::L7);
} }

3
lib/Target/Sparc/SparcRegisterInfo.td
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@@ -26,6 +26,9 @@ let Namespace = "V8" in {
def I0 : Ri<24>; def I1 : Ri<25>; def I2 : Ri<26>; def I3 : Ri<27>; def I0 : Ri<24>; def I1 : Ri<25>; def I2 : Ri<26>; def I3 : Ri<27>;
def I4 : Ri<28>; def I5 : Ri<29>; def I6 : Ri<30>; def I7 : Ri<31>; def I4 : Ri<28>; def I5 : Ri<29>; def I6 : Ri<30>; def I7 : Ri<31>;
// Standard register aliases.
def SP : Ri<14>; def FP : Ri<30>;
// Floating-point registers? // Floating-point registers?
// ... // ...
} }

20
lib/Target/SparcV8/SparcV8RegisterInfo.cpp
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@@ -13,7 +13,10 @@
#include "SparcV8.h" #include "SparcV8.h"
#include "SparcV8RegisterInfo.h" #include "SparcV8RegisterInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Type.h" #include "llvm/Type.h"
#include "Support/STLExtras.h"
using namespace llvm; using namespace llvm;
SparcV8RegisterInfo::SparcV8RegisterInfo() SparcV8RegisterInfo::SparcV8RegisterInfo()
@@ -60,18 +63,23 @@ SparcV8RegisterInfo::eliminateFrameIndex(MachineFunction &MF,
abort(); abort();
} }
void SparcV8RegisterInfo::processFunctionBeforeFrameFinalized( void SparcV8RegisterInfo::
MachineFunction &MF) const { processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
abort();
}
void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const { void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
abort(); MachineBasicBlock &MBB = MF.front();
// Eventually this should emit the correct save instruction based on the
// number of bytes in the frame. For now we just hardcode it.
BuildMI(MBB, MBB.begin(), V8::SAVEi, 2, V8::SP).addImm(-122).addReg(V8::SP);
} }
void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF, void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const { MachineBasicBlock &MBB) const {
abort(); MachineBasicBlock::iterator MBBI = prior(MBB.end());
assert(MBBI->getOpcode() == V8::JMPLi &&
"Can only put epilog before return instruction!");
BuildMI(MBB, MBBI, V8::RESTOREi, 2, V8::O0).addImm(0).addReg(V8::L7);
} }

3
lib/Target/SparcV8/SparcV8RegisterInfo.td
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@@ -26,6 +26,9 @@ let Namespace = "V8" in {
def I0 : Ri<24>; def I1 : Ri<25>; def I2 : Ri<26>; def I3 : Ri<27>; def I0 : Ri<24>; def I1 : Ri<25>; def I2 : Ri<26>; def I3 : Ri<27>;
def I4 : Ri<28>; def I5 : Ri<29>; def I6 : Ri<30>; def I7 : Ri<31>; def I4 : Ri<28>; def I5 : Ri<29>; def I6 : Ri<30>; def I7 : Ri<31>;
// Standard register aliases.
def SP : Ri<14>; def FP : Ri<30>;
// Floating-point registers? // Floating-point registers?
// ... // ...
} }