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[PowerPC] Merge/rename PPC fixup types
Now that fixup_ppc_ha16 and fixup_ppc_lo16 are being treated exactly the same everywhere, it no longer makes sense to have two fixup types. This patch merges them both into a single type fixup_ppc_half16, and renames fixup_ppc_lo16_ds to fixup_ppc_half16ds for consistency. (The half16 and half16ds names are taken from the description of relocation types in the PowerPC ABI.) No change in code generation expected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182092 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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c299ad32c8
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@ -37,13 +37,9 @@ static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) {
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return Value & 0xfffc;
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case PPC::fixup_ppc_br24:
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return Value & 0x3fffffc;
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#if 0
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case PPC::fixup_ppc_hi16:
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#endif
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case PPC::fixup_ppc_ha16:
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case PPC::fixup_ppc_lo16:
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case PPC::fixup_ppc_half16:
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return Value & 0xffff;
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case PPC::fixup_ppc_lo16_ds:
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case PPC::fixup_ppc_half16ds:
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return Value & 0xfffc;
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}
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}
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@ -55,9 +51,8 @@ static unsigned getFixupKindNumBytes(unsigned Kind) {
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case FK_Data_1:
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return 1;
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case FK_Data_2:
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case PPC::fixup_ppc_ha16:
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case PPC::fixup_ppc_lo16:
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case PPC::fixup_ppc_lo16_ds:
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case PPC::fixup_ppc_half16:
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case PPC::fixup_ppc_half16ds:
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return 2;
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case FK_Data_4:
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case PPC::fixup_ppc_brcond14:
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@ -98,9 +93,8 @@ public:
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// name offset bits flags
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{ "fixup_ppc_br24", 6, 24, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_ppc_brcond14", 16, 14, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_ppc_lo16", 0, 16, 0 },
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{ "fixup_ppc_ha16", 0, 16, 0 },
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{ "fixup_ppc_lo16_ds", 0, 14, 0 },
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{ "fixup_ppc_half16", 0, 16, 0 },
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{ "fixup_ppc_half16ds", 0, 14, 0 },
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{ "fixup_ppc_tlsreg", 0, 0, 0 },
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{ "fixup_ppc_nofixup", 0, 0, 0 }
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};
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@ -81,8 +81,7 @@ unsigned PPCELFObjectWriter::getRelocTypeInner(const MCValue &Target,
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case PPC::fixup_ppc_brcond14:
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Type = ELF::R_PPC_ADDR14; // XXX: or BRNTAKEN?_
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break;
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case PPC::fixup_ppc_ha16:
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case PPC::fixup_ppc_lo16:
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case PPC::fixup_ppc_half16:
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switch (Modifier) {
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default: llvm_unreachable("Unsupported Modifier");
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case MCSymbolRefExpr::VK_PPC_TPREL16_HA:
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@ -134,7 +133,7 @@ unsigned PPCELFObjectWriter::getRelocTypeInner(const MCValue &Target,
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break;
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}
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break;
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case PPC::fixup_ppc_lo16_ds:
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case PPC::fixup_ppc_half16ds:
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switch (Modifier) {
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default: llvm_unreachable("Unsupported Modifier");
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case MCSymbolRefExpr::VK_None:
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@ -25,17 +25,13 @@ enum Fixups {
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/// branches.
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fixup_ppc_brcond14,
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/// fixup_ppc_lo16 - A 16-bit fixup corresponding to lo16(_foo) for instrs
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/// like 'li'.
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fixup_ppc_lo16,
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/// fixup_ppc_half16 - A 16-bit fixup corresponding to lo16(_foo)
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/// or ha16(_foo) for instrs like 'li' or 'addis'.
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fixup_ppc_half16,
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/// fixup_ppc_ha16 - A 16-bit fixup corresponding to ha16(_foo) for instrs
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/// like 'lis'.
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fixup_ppc_ha16,
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/// fixup_ppc_lo16_ds - A 14-bit fixup corresponding to lo16(_foo) with
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/// fixup_ppc_half16ds - A 14-bit fixup corresponding to lo16(_foo) with
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/// implied 2 zero bits for instrs like 'std'.
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fixup_ppc_lo16_ds,
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fixup_ppc_half16ds,
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/// fixup_ppc_tlsreg - Insert thread-pointer register number.
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fixup_ppc_tlsreg,
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@ -143,7 +143,7 @@ unsigned PPCMCCodeEmitter::getHA16Encoding(const MCInst &MI, unsigned OpNo,
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// Add a fixup for the branch target.
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Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_ha16));
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(MCFixupKind)PPC::fixup_ppc_half16));
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return 0;
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}
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@ -154,7 +154,7 @@ unsigned PPCMCCodeEmitter::getLO16Encoding(const MCInst &MI, unsigned OpNo,
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// Add a fixup for the branch target.
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Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_lo16));
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(MCFixupKind)PPC::fixup_ppc_half16));
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return 0;
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}
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@ -171,7 +171,7 @@ unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
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// Add a fixup for the displacement field.
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Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_lo16));
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(MCFixupKind)PPC::fixup_ppc_half16));
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return RegBits;
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}
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@ -189,7 +189,7 @@ unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
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// Add a fixup for the displacement field.
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Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_lo16_ds));
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(MCFixupKind)PPC::fixup_ppc_half16ds));
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return RegBits;
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}
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@ -8,77 +8,77 @@
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# FIXME: .TOC.@tocbase
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# CHECK: li 3, target@l # encoding: [0x38,0x60,A,A]
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# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_lo16
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# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0
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li 3, target@l
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# CHECK: addis 3, 3, target@ha # encoding: [0x3c,0x63,A,A]
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# CHECK-NEXT: # fixup A - offset: 2, value: target@ha, kind: fixup_ppc_ha16
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# CHECK-NEXT: # fixup A - offset: 2, value: target@ha, kind: fixup_ppc_half16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HA target 0x0
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addis 3, 3, target@ha
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# CHECK: lis 3, target@ha # encoding: [0x3c,0x60,A,A]
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# CHECK-NEXT: # fixup A - offset: 2, value: target@ha, kind: fixup_ppc_ha16
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# CHECK-NEXT: # fixup A - offset: 2, value: target@ha, kind: fixup_ppc_half16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HA target 0x0
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lis 3, target@ha
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# CHECK: addi 4, 3, target@l # encoding: [0x38,0x83,A,A]
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# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_lo16
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# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0
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addi 4, 3, target@l
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# CHECK: li 3, target@ha # encoding: [0x38,0x60,A,A]
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# CHECK-NEXT: # fixup A - offset: 2, value: target@ha, kind: fixup_ppc_lo16
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# CHECK-NEXT: # fixup A - offset: 2, value: target@ha, kind: fixup_ppc_half16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HA target 0x0
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li 3, target@ha
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# CHECK: lis 3, target@l # encoding: [0x3c,0x60,A,A]
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# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_ha16
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# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0
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lis 3, target@l
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# CHECK: li 3, target # encoding: [0x38,0x60,A,A]
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# CHECK-NEXT: # fixup A - offset: 2, value: target, kind: fixup_ppc_lo16
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# CHECK-NEXT: # fixup A - offset: 2, value: target, kind: fixup_ppc_half16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16 target 0x0
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li 3, target
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# CHECK: lis 3, target # encoding: [0x3c,0x60,A,A]
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# CHECK-NEXT: # fixup A - offset: 2, value: target, kind: fixup_ppc_ha16
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# CHECK-NEXT: # fixup A - offset: 2, value: target, kind: fixup_ppc_half16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16 target 0x0
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lis 3, target
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# CHECK: lwz 1, target@l(3) # encoding: [0x80,0x23,A,A]
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# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_lo16
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# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0
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lwz 1, target@l(3)
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# CHECK: ld 1, target@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00]
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# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_lo16_ds
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# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16ds
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO_DS target 0x0
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ld 1, target@l(3)
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# CHECK: ld 1, target@toc(2) # encoding: [0xe8,0x22,A,0bAAAAAA00]
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# CHECK-NEXT: # fixup A - offset: 2, value: target@toc, kind: fixup_ppc_lo16_ds
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# CHECK-NEXT: # fixup A - offset: 2, value: target@toc, kind: fixup_ppc_half16ds
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_DS target 0x0
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ld 1, target@toc(2)
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# CHECK: addis 3, 2, target@toc@ha # encoding: [0x3c,0x62,A,A]
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# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@ha, kind: fixup_ppc_ha16
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# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@ha, kind: fixup_ppc_half16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_HA target 0x0
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addis 3, 2, target@toc@ha
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# CHECK: addi 4, 3, target@toc@l # encoding: [0x38,0x83,A,A]
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# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_lo16
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# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_half16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO target 0x0
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addi 4, 3, target@toc@l
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# CHECK: lwz 1, target@toc@l(3) # encoding: [0x80,0x23,A,A]
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# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_lo16
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# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_half16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO target 0x0
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lwz 1, target@toc@l(3)
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# CHECK: ld 1, target@toc@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00]
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# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_lo16_ds
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# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_half16ds
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO_DS target 0x0
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ld 1, target@toc@l(3)
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@ -86,55 +86,55 @@
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# CHECK: addis 3, 2, target@tprel@ha # encoding: [0x3c,0x62,A,A]
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# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel@ha, kind: fixup_ppc_ha16
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# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel@ha, kind: fixup_ppc_half16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_HA target 0x0
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addis 3, 2, target@tprel@ha
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# CHECK: addi 3, 3, target@tprel@l # encoding: [0x38,0x63,A,A]
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# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel@l, kind: fixup_ppc_lo16
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# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel@l, kind: fixup_ppc_half16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_LO target 0x0
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addi 3, 3, target@tprel@l
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# CHECK: addis 3, 2, target@dtprel@ha # encoding: [0x3c,0x62,A,A]
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# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel@ha, kind: fixup_ppc_ha16
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# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel@ha, kind: fixup_ppc_half16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_HA target 0x0
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addis 3, 2, target@dtprel@ha
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# CHECK: addi 3, 3, target@dtprel@l # encoding: [0x38,0x63,A,A]
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# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel@l, kind: fixup_ppc_lo16
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# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel@l, kind: fixup_ppc_half16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_LO target 0x0
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addi 3, 3, target@dtprel@l
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# CHECK: addis 3, 2, target@got@tprel@ha # encoding: [0x3c,0x62,A,A]
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# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tprel@ha, kind: fixup_ppc_ha16
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# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tprel@ha, kind: fixup_ppc_half16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_HA target 0x0
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addis 3, 2, target@got@tprel@ha
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# CHECK: ld 1, target@got@tprel@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00]
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# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tprel@l, kind: fixup_ppc_lo16_ds
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# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tprel@l, kind: fixup_ppc_half16ds
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_LO_DS target 0x0
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ld 1, target@got@tprel@l(3)
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# CHECK: addis 3, 2, target@got@tlsgd@ha # encoding: [0x3c,0x62,A,A]
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# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsgd@ha, kind: fixup_ppc_ha16
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# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsgd@ha, kind: fixup_ppc_half16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSGD16_HA target 0x0
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addis 3, 2, target@got@tlsgd@ha
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# CHECK: addi 3, 3, target@got@tlsgd@l # encoding: [0x38,0x63,A,A]
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# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsgd@l, kind: fixup_ppc_lo16
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# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsgd@l, kind: fixup_ppc_half16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSGD16_LO target 0x0
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addi 3, 3, target@got@tlsgd@l
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# CHECK: addis 3, 2, target@got@tlsld@ha # encoding: [0x3c,0x62,A,A]
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# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsld@ha, kind: fixup_ppc_ha16
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# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsld@ha, kind: fixup_ppc_half16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSLD16_HA target 0x0
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addis 3, 2, target@got@tlsld@ha
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# CHECK: addi 3, 3, target@got@tlsld@l # encoding: [0x38,0x63,A,A]
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# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsld@l, kind: fixup_ppc_lo16
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# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsld@l, kind: fixup_ppc_half16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSLD16_LO target 0x0
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addi 3, 3, target@got@tlsld@l
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