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[X86] Remove 16-bit and 32-bit offset jump instructions from the AsmParser. We always select the 8-bit size and let the assembler backend relax to the larger size.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225243 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2015-01-06 04:23:57 +00:00
parent 1299ae2403
commit e16c86e524
1 changed files with 2 additions and 2 deletions
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4
lib/Target/X86/X86InstrControl.td
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@ -59,7 +59,7 @@ let isTerminator = 1, isReturn = 1, isBarrier = 1,
let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in {
def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
"jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>;
let hasSideEffects = 0 in {
let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in {
def JMP_2 : Ii16PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
"jmp\t$dst", [], IIC_JMP_REL>, OpSize16;
def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
@ -72,7 +72,7 @@ let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in {
multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm,
[(X86brcond bb:$dst, Cond, EFLAGS)], IIC_Jcc>;
let hasSideEffects = 0 in {
let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in {
def _2 : Ii16PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
[], IIC_Jcc>, OpSize16, TB;
def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,