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Jakob's review of the basic register allocator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117384 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -21,6 +21,9 @@
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using namespace llvm;
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// Merge a LiveInterval's segments. Guarantee no overlaps.
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//
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// Consider coalescing adjacent segments to save space, even though it makes
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// extraction more complicated.
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void LiveIntervalUnion::unify(LiveInterval &lvr) {
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// Add this live virtual register to the union
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LiveVirtRegs::iterator pos = std::upper_bound(lvrs_.begin(), lvrs_.end(),
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@ -34,19 +37,21 @@ void LiveIntervalUnion::unify(LiveInterval &lvr) {
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LiveSegment segment(lvrI->start, lvrI->end, lvr);
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segPos = segments_.insert(segPos, segment);
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assert(*segPos == segment && "need equal val for equal key");
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#ifndef NDEBUG
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// check for overlap (inductively)
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if (segPos != segments_.begin()) {
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SegmentIter prevPos = segPos;
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--prevPos;
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assert(prevPos->end <= segment.start && "overlapping segments" );
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}
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SegmentIter nextPos = segPos;
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++nextPos;
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if (nextPos != segments_.end())
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assert(segment.end <= nextPos->start && "overlapping segments" );
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#endif // NDEBUG
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}
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}
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namespace {
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// Keep LVRs sorted for fast membership test and extraction.
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struct LessReg
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: public std::binary_function<LiveInterval*, LiveInterval*, bool> {
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bool operator()(const LiveInterval *left, const LiveInterval *right) const {
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return left->reg < right->reg;
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}
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};
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// Low-level helper to find the first segment in the range [segI,segEnd) that
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// intersects with a live virtual register segment, or segI.start >= lvr.end
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//
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@ -67,10 +72,8 @@ struct LessReg
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// Assuming intervals are disjoint, if an intersection exists, it must be the
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// segment found or immediately behind it. We continue reverse iterating to
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// return the first overlap.
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//
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// FIXME: support extract(), handle tombstones of extracted lvrs.
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typedef LiveIntervalUnion::SegmentIter SegmentIter;
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SegmentIter upperBound(SegmentIter segBegin,
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static SegmentIter upperBound(SegmentIter segBegin,
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SegmentIter segEnd,
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const LiveRange &lvrSeg) {
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assert(lvrSeg.end > segBegin->start && "segment iterator precondition");
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@ -84,7 +87,6 @@ SegmentIter upperBound(SegmentIter segBegin,
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}
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return segI;
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}
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} // end anonymous namespace
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// Private interface accessed by Query.
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//
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@ -23,13 +23,16 @@
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namespace llvm {
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// A LiveSegment is a copy of a LiveRange object used within
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// LiveIntervalUnion. LiveSegment additionally contains a pointer to its
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// original live virtual register (LiveInterval). This allows quick lookup of
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// the live virtual register as we iterate over live segments in a union. Note
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// that LiveRange is misnamed and actually represents only a single contiguous
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// interval within a virtual register's liveness. To limit confusion, in this
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// file we refer it as a live segment.
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/// A LiveSegment is a copy of a LiveRange object used within
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/// LiveIntervalUnion. LiveSegment additionally contains a pointer to its
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/// original live virtual register (LiveInterval). This allows quick lookup of
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/// the live virtual register as we iterate over live segments in a union. Note
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/// that LiveRange is misnamed and actually represents only a single contiguous
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/// interval within a virtual register's liveness. To limit confusion, in this
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/// file we refer it as a live segment.
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///
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/// Note: This currently represents a half-open interval [start,end).
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/// If LiveRange is modified to represent a closed interval, so should this.
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struct LiveSegment {
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SlotIndex start;
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SlotIndex end;
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@ -46,16 +49,10 @@ struct LiveSegment {
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return !operator==(ls);
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}
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bool operator<(const LiveSegment &ls) const {
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return start < ls.start || (start == ls.start && end < ls.end);
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}
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// Order segments by starting point only--we expect them to be disjoint.
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bool operator<(const LiveSegment &ls) const { return start < ls.start; }
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};
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/// Compare a live virtual register segment to a LiveIntervalUnion segment.
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inline bool overlap(const LiveRange &lvrSeg, const LiveSegment &liuSeg) {
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return lvrSeg.start < liuSeg.end && liuSeg.start < lvrSeg.end;
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}
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inline bool operator<(SlotIndex V, const LiveSegment &ls) {
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return V < ls.start;
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}
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@ -64,6 +61,11 @@ inline bool operator<(const LiveSegment &ls, SlotIndex V) {
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return ls.start < V;
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}
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/// Compare a live virtual register segment to a LiveIntervalUnion segment.
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inline bool overlap(const LiveRange &lvrSeg, const LiveSegment &liuSeg) {
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return lvrSeg.start < liuSeg.end && liuSeg.start < lvrSeg.end;
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}
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/// Union of live intervals that are strong candidates for coalescing into a
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/// single register (either physical or virtual depending on the context). We
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/// expect the constituent live intervals to be disjoint, although we may
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@ -100,13 +102,18 @@ private:
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public:
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// default ctor avoids placement new
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LiveIntervalUnion() : repReg_(0) {}
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// Initialize the union by associating it with a representative register
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// number.
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void init(unsigned repReg) { repReg_ = repReg; }
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// Iterate over all segments in the union of live virtual registers ordered
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// by their starting position.
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SegmentIter begin() { return segments_.begin(); }
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SegmentIter end() { return segments_.end(); }
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/// FIXME: !!!!!!!!!!! Keeps a non-const ref
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// Add a live virtual register to this union and merge its segments.
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// Holds a nonconst reference to the LVR for later maniplution.
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void unify(LiveInterval &lvr);
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// FIXME: needed by RegAllocGreedy
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@ -37,17 +37,29 @@
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#ifndef LLVM_CODEGEN_REGALLOCBASE
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#define LLVM_CODEGEN_REGALLOCBASE
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#include "LiveIntervalUnion.h"
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#include "VirtRegMap.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/ADT/OwningPtr.h"
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#include <vector>
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#include <queue>
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namespace llvm {
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template<typename T> class SmallVectorImpl;
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class TargetRegisterInfo;
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class VirtRegMap;
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class LiveIntervals;
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// Heuristic that determines the priority of assigning virtual to physical
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// registers. The main impact of the heuristic is expected to be compile time.
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// The default is to simply compare spill weights.
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struct LessSpillWeightPriority
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: public std::binary_function<LiveInterval,LiveInterval, bool> {
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bool operator()(const LiveInterval *left, const LiveInterval *right) const {
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return left->weight < right->weight;
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}
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};
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// Forward declare a priority queue of live virtual registers. If an
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// implementation needs to prioritize by anything other than spill weight, then
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// this will become an abstract base class with virtual calls to push/get.
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class LiveVirtRegQueue;
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/// RegAllocBase provides the register allocation driver and interface that can
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/// be extended to add interesting heuristics.
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@ -58,9 +70,6 @@ class VirtRegMap;
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/// standard comparator.
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class RegAllocBase {
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protected:
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typedef SmallVector<LiveInterval*, 4> LiveVirtRegs;
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typedef LiveVirtRegs::iterator LVRIter;
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// Array of LiveIntervalUnions indexed by physical register.
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class LIUArray {
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unsigned nRegs_;
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@ -92,18 +101,20 @@ protected:
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// A RegAlloc pass should call this before allocatePhysRegs.
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void init(const TargetRegisterInfo &tri, VirtRegMap &vrm, LiveIntervals &lis);
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// The top-level driver. Specialize with the comparator that determines the
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// priority of assigning live virtual registers. The output is a VirtRegMap
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// that us updated with physical register assignments.
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template<typename LICompare>
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void allocatePhysRegs(LICompare liCompare);
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// The top-level driver. The output is a VirtRegMap that us updated with
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// physical register assignments.
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//
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// If an implementation wants to override the LiveInterval comparator, we
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// should modify this interface to allow passing in an instance derived from
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// LiveVirtRegQueue.
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void allocatePhysRegs();
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// A RegAlloc pass should override this to provide the allocation heuristics.
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// Each call must guarantee forward progess by returning an available
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// PhysReg or new set of split LiveVirtRegs. It is up to the splitter to
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// Each call must guarantee forward progess by returning an available PhysReg
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// or new set of split live virtual registers. It is up to the splitter to
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// converge quickly toward fully spilled live ranges.
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virtual unsigned selectOrSplit(LiveInterval &lvr,
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LiveVirtRegs &splitLVRs) = 0;
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SmallVectorImpl<LiveInterval*> &splitLVRs) = 0;
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// A RegAlloc pass should call this when PassManager releases its memory.
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virtual void releaseMemory();
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@ -113,69 +124,9 @@ protected:
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bool checkPhysRegInterference(LiveIntervalUnion::Query &query, unsigned preg);
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private:
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template<typename PQ>
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void seedLiveVirtRegs(PQ &lvrQ);
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void seedLiveVirtRegs(LiveVirtRegQueue &lvrQ);
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};
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// Heuristic that determines the priority of assigning virtual to physical
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// registers. The main impact of the heuristic is expected to be compile time.
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// The default is to simply compare spill weights.
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struct LessSpillWeightPriority
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: public std::binary_function<LiveInterval,LiveInterval, bool> {
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bool operator()(const LiveInterval *left, const LiveInterval *right) const {
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return left->weight < right->weight;
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}
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};
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// Visit all the live virtual registers. If they are already assigned to a
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// physical register, unify them with the corresponding LiveIntervalUnion,
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// otherwise push them on the priority queue for later assignment.
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template<typename PQ>
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void RegAllocBase::seedLiveVirtRegs(PQ &lvrQ) {
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for (LiveIntervals::iterator liItr = lis_->begin(), liEnd = lis_->end();
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liItr != liEnd; ++liItr) {
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unsigned reg = liItr->first;
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LiveInterval &li = *liItr->second;
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if (TargetRegisterInfo::isPhysicalRegister(reg)) {
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physReg2liu_[reg].unify(li);
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}
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else {
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lvrQ.push(&li);
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}
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}
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}
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// Top-level driver to manage the queue of unassigned LiveVirtRegs and call the
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// selectOrSplit implementation.
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template<typename LICompare>
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void RegAllocBase::allocatePhysRegs(LICompare liCompare) {
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typedef std::priority_queue
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<LiveInterval*, std::vector<LiveInterval*>, LICompare> LiveVirtRegQueue;
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LiveVirtRegQueue lvrQ(liCompare);
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seedLiveVirtRegs(lvrQ);
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while (!lvrQ.empty()) {
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LiveInterval *lvr = lvrQ.top();
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lvrQ.pop();
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LiveVirtRegs splitLVRs;
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unsigned availablePhysReg = selectOrSplit(*lvr, splitLVRs);
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if (availablePhysReg) {
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assert(splitLVRs.empty() && "inconsistent splitting");
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assert(!vrm_->hasPhys(lvr->reg) && "duplicate vreg in interval unions");
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vrm_->assignVirt2Phys(lvr->reg, availablePhysReg);
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physReg2liu_[availablePhysReg].unify(*lvr);
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}
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else {
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for (LVRIter lvrI = splitLVRs.begin(), lvrEnd = splitLVRs.end();
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lvrI != lvrEnd; ++lvrI ) {
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assert(TargetRegisterInfo::isVirtualRegister((*lvrI)->reg) &&
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"expect split value in virtual register");
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lvrQ.push(*lvrI);
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}
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}
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}
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}
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} // end namespace llvm
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#endif // !defined(LLVM_CODEGEN_REGALLOCBASE)
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "LiveIntervalUnion.h"
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#include "RegAllocBase.h"
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#include "RenderMachineFunction.h"
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#include "Spiller.h"
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@ -33,6 +34,14 @@
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "VirtRegMap.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include <vector>
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#include <queue>
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using namespace llvm;
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static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
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@ -72,7 +81,8 @@ public:
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virtual void releaseMemory();
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virtual unsigned selectOrSplit(LiveInterval &lvr, LiveVirtRegs &splitLVRs);
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virtual unsigned selectOrSplit(LiveInterval &lvr,
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SmallVectorImpl<LiveInterval*> &splitLVRs);
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/// Perform register allocation.
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virtual bool runOnMachineFunction(MachineFunction &mf);
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@ -101,7 +111,7 @@ INITIALIZE_PASS_DEPENDENCY(RenderMachineFunction)
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#endif
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INITIALIZE_PASS_END(RABasic, "basic-regalloc",
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"Basic Register Allocator", false, false)
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#endif // INITIALIZE_PASS
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#endif // disable INITIALIZE_PASS
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RABasic::RABasic(): MachineFunctionPass(ID) {
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initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
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@ -168,6 +178,79 @@ void RegAllocBase::releaseMemory() {
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physReg2liu_.clear();
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}
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namespace llvm {
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/// This class defines a queue of live virtual registers prioritized by spill
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/// weight. The heaviest vreg is popped first.
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///
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/// Currently, this is trivial wrapper that gives us an opaque type in the
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/// header, but we may later give it a virtual interface for register allocators
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/// to override the priority queue comparator.
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class LiveVirtRegQueue {
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typedef std::priority_queue
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<LiveInterval*, std::vector<LiveInterval*>, LessSpillWeightPriority> PQ;
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PQ pq_;
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public:
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// Is the queue empty?
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bool empty() { return pq_.empty(); }
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// Get the highest priority lvr (top + pop)
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LiveInterval *get() {
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LiveInterval *lvr = pq_.top();
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pq_.pop();
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return lvr;
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}
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// Add this lvr to the queue
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void push(LiveInterval *lvr) {
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pq_.push(lvr);
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}
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};
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} // end namespace llvm
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// Visit all the live virtual registers. If they are already assigned to a
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// physical register, unify them with the corresponding LiveIntervalUnion,
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// otherwise push them on the priority queue for later assignment.
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void RegAllocBase::seedLiveVirtRegs(LiveVirtRegQueue &lvrQ) {
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for (LiveIntervals::iterator liItr = lis_->begin(), liEnd = lis_->end();
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liItr != liEnd; ++liItr) {
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unsigned reg = liItr->first;
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LiveInterval &li = *liItr->second;
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if (TargetRegisterInfo::isPhysicalRegister(reg)) {
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physReg2liu_[reg].unify(li);
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}
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else {
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lvrQ.push(&li);
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}
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}
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}
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// Top-level driver to manage the queue of unassigned LiveVirtRegs and call the
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// selectOrSplit implementation.
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void RegAllocBase::allocatePhysRegs() {
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LiveVirtRegQueue lvrQ;
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seedLiveVirtRegs(lvrQ);
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while (!lvrQ.empty()) {
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LiveInterval *lvr = lvrQ.get();
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typedef SmallVector<LiveInterval*, 4> LVRVec;
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LVRVec splitLVRs;
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unsigned availablePhysReg = selectOrSplit(*lvr, splitLVRs);
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if (availablePhysReg) {
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assert(splitLVRs.empty() && "inconsistent splitting");
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assert(!vrm_->hasPhys(lvr->reg) && "duplicate vreg in interval unions");
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vrm_->assignVirt2Phys(lvr->reg, availablePhysReg);
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physReg2liu_[availablePhysReg].unify(*lvr);
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}
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else {
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for (LVRVec::iterator lvrI = splitLVRs.begin(), lvrEnd = splitLVRs.end();
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lvrI != lvrEnd; ++lvrI) {
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assert(TargetRegisterInfo::isVirtualRegister((*lvrI)->reg) &&
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"expect split value in virtual register");
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lvrQ.push(*lvrI);
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}
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}
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}
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}
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// Check if this live virtual reg interferes with a physical register. If not,
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// then check for interference on each register that aliases with the physical
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// register.
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@ -201,7 +284,8 @@ bool RegAllocBase::checkPhysRegInterference(LiveIntervalUnion::Query &query,
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// available register. So, the number of interference tests in the worst case is
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// |vregs| * |machineregs|. And since the number of interference tests is
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// minimal, there is no value in caching them.
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unsigned RABasic::selectOrSplit(LiveInterval &lvr, LiveVirtRegs &splitLVRs) {
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unsigned RABasic::selectOrSplit(LiveInterval &lvr,
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SmallVectorImpl<LiveInterval*> &splitLVRs) {
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// Check for an available reg in this class.
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const TargetRegisterClass *trc = mri_->getRegClass(lvr.reg);
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for (TargetRegisterClass::iterator trcI = trc->allocation_order_begin(*mf_),
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@ -238,7 +322,7 @@ bool RABasic::runOnMachineFunction(MachineFunction &mf) {
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spiller_.reset(createSpiller(*this, *mf_, *vrm_));
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allocatePhysRegs(LessSpillWeightPriority());
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allocatePhysRegs();
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// Diagnostic output before rewriting
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DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *vrm_ << "\n");
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@ -249,6 +333,9 @@ bool RABasic::runOnMachineFunction(MachineFunction &mf) {
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// Run rewriter
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std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter());
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rewriter->runOnMachineFunction(*mf_, *vrm_, lis_);
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// The pass output is in VirtRegMap. Release all the transient data.
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releaseMemory();
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return true;
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}
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