mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-08 18:30:04 +00:00
[Hexagon] Cleaning up definition formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228593 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
parent
af30d1e97a
commit
e17141f9f3
@ -256,7 +256,6 @@ def: Pat<(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, (i32 IntRegs:$src2))),
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(i32 IntRegs:$src1))), 0)))),
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(C2_muxii (S2_tstbit_r IntRegs:$src1, IntRegs:$src2), 1, 0)>;
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//===----------------------------------------------------------------------===//
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// ALU32 -
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//===----------------------------------------------------------------------===//
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@ -1760,6 +1759,7 @@ def S4_parity: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
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let Inst{12-8} = Rt;
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let Inst{4-0} = Rd;
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}
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// Add and accumulate.
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// Rd=add(Rs,add(Ru,#s6))
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let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 6,
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@ -1807,7 +1807,7 @@ def S4_subaddi: ALU64Inst <(outs IntRegs:$Rd),
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let Inst{7-5} = s6{2-0};
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let Inst{4-0} = Ru;
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}
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// Extract bitfield
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// Rdd=extract(Rss,#u6,#U6)
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// Rdd=extract(Rss,Rtt)
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@ -1857,9 +1857,10 @@ def M4_xor_xacc
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let IClass = 0b1100;
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let Inst{27-23} = 0b10101;
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let Inst{27-22} = 0b101010;
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let Inst{20-16} = Rss;
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let Inst{12-8} = Rtt;
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let Inst{7-5} = 0b000;
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let Inst{4-0} = Rxx;
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}
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@ -1910,7 +1911,6 @@ def S4_vrcrotate_acc
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let Inst{4-0} = Rxx;
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}
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// Vector reduce conditional negate halfwords
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let hasSideEffects = 0 in
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def S2_vrcnegh
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@ -2348,7 +2348,6 @@ def M4_pmpyw_acc : T_XTYPE_mpy64_acc < "pmpyw", "^", 0b001, 0b111, 0, 0, 0>;
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// XTYPE/MPY -
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// ALU64/Vector compare
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//===----------------------------------------------------------------------===//
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@ -2743,40 +2742,40 @@ let isExtendable = 1, opExtendable = 1, isExtentSigned = 0,
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multiclass MemOpi_u5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
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InstHexagon MI, SDNode OpNode> {
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let AddedComplexity = 180 in
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def : Pat < (stOp (OpNode (ldOp IntRegs:$addr), u5ImmPred:$addend),
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IntRegs:$addr),
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(MI IntRegs:$addr, #0, u5ImmPred:$addend )>;
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def: Pat<(stOp (OpNode (ldOp IntRegs:$addr), u5ImmPred:$addend),
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IntRegs:$addr),
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(MI IntRegs:$addr, 0, u5ImmPred:$addend)>;
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let AddedComplexity = 190 in
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def : Pat <(stOp (OpNode (ldOp (add IntRegs:$base, ExtPred:$offset)),
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u5ImmPred:$addend),
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(add IntRegs:$base, ExtPred:$offset)),
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(MI IntRegs:$base, ExtPred:$offset, u5ImmPred:$addend)>;
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def: Pat<(stOp (OpNode (ldOp (add IntRegs:$base, ExtPred:$offset)),
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u5ImmPred:$addend),
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(add IntRegs:$base, ExtPred:$offset)),
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(MI IntRegs:$base, ExtPred:$offset, u5ImmPred:$addend)>;
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}
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multiclass MemOpi_u5ALUOp<PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
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InstHexagon addMI, InstHexagon subMI> {
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defm : MemOpi_u5Pats<ldOp, stOp, ExtPred, addMI, add>;
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defm : MemOpi_u5Pats<ldOp, stOp, ExtPred, subMI, sub>;
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defm: MemOpi_u5Pats<ldOp, stOp, ExtPred, addMI, add>;
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defm: MemOpi_u5Pats<ldOp, stOp, ExtPred, subMI, sub>;
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}
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multiclass MemOpi_u5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
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// Half Word
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defm : MemOpi_u5ALUOp <ldOpHalf, truncstorei16, u6_1ExtPred,
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L4_iadd_memoph_io, L4_isub_memoph_io>;
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defm: MemOpi_u5ALUOp <ldOpHalf, truncstorei16, u6_1ExtPred,
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L4_iadd_memoph_io, L4_isub_memoph_io>;
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// Byte
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defm : MemOpi_u5ALUOp <ldOpByte, truncstorei8, u6ExtPred,
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L4_iadd_memopb_io, L4_isub_memopb_io>;
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defm: MemOpi_u5ALUOp <ldOpByte, truncstorei8, u6ExtPred,
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L4_iadd_memopb_io, L4_isub_memopb_io>;
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}
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let Predicates = [HasV4T, UseMEMOP] in {
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defm : MemOpi_u5ExtType<zextloadi8, zextloadi16>; // zero extend
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defm : MemOpi_u5ExtType<sextloadi8, sextloadi16>; // sign extend
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defm : MemOpi_u5ExtType<extloadi8, extloadi16>; // any extend
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defm: MemOpi_u5ExtType<zextloadi8, zextloadi16>; // zero extend
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defm: MemOpi_u5ExtType<sextloadi8, sextloadi16>; // sign extend
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defm: MemOpi_u5ExtType<extloadi8, extloadi16>; // any extend
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// Word
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defm : MemOpi_u5ALUOp <load, store, u6_2ExtPred, L4_iadd_memopw_io,
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L4_isub_memopw_io>;
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defm: MemOpi_u5ALUOp <load, store, u6_2ExtPred, L4_iadd_memopw_io,
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L4_isub_memopw_io>;
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}
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//===----------------------------------------------------------------------===//
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@ -2790,33 +2789,32 @@ multiclass MemOpi_m5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
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PatLeaf immPred, ComplexPattern addrPred,
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SDNodeXForm xformFunc, InstHexagon MI> {
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let AddedComplexity = 190 in
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def : Pat <(stOp (add (ldOp IntRegs:$addr), immPred:$subend),
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IntRegs:$addr),
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(MI IntRegs:$addr, #0, (xformFunc immPred:$subend) )>;
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def: Pat<(stOp (add (ldOp IntRegs:$addr), immPred:$subend), IntRegs:$addr),
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(MI IntRegs:$addr, 0, (xformFunc immPred:$subend))>;
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let AddedComplexity = 195 in
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def : Pat<(stOp (add (ldOp (add IntRegs:$base, extPred:$offset)),
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immPred:$subend),
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(add IntRegs:$base, extPred:$offset)),
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(MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$subend))>;
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def: Pat<(stOp (add (ldOp (add IntRegs:$base, extPred:$offset)),
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immPred:$subend),
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(add IntRegs:$base, extPred:$offset)),
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(MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$subend))>;
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}
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multiclass MemOpi_m5ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
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// Half Word
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defm : MemOpi_m5Pats <ldOpHalf, truncstorei16, u6_1ExtPred, m5HImmPred,
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defm: MemOpi_m5Pats <ldOpHalf, truncstorei16, u6_1ExtPred, m5HImmPred,
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ADDRriU6_1, MEMOPIMM_HALF, L4_isub_memoph_io>;
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// Byte
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defm : MemOpi_m5Pats <ldOpByte, truncstorei8, u6ExtPred, m5BImmPred,
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defm: MemOpi_m5Pats <ldOpByte, truncstorei8, u6ExtPred, m5BImmPred,
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ADDRriU6_0, MEMOPIMM_BYTE, L4_isub_memopb_io>;
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}
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let Predicates = [HasV4T, UseMEMOP] in {
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defm : MemOpi_m5ExtType<zextloadi8, zextloadi16>; // zero extend
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defm : MemOpi_m5ExtType<sextloadi8, sextloadi16>; // sign extend
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defm : MemOpi_m5ExtType<extloadi8, extloadi16>; // any extend
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defm: MemOpi_m5ExtType<zextloadi8, zextloadi16>; // zero extend
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defm: MemOpi_m5ExtType<sextloadi8, sextloadi16>; // sign extend
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defm: MemOpi_m5ExtType<extloadi8, extloadi16>; // any extend
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// Word
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defm : MemOpi_m5Pats <load, store, u6_2ExtPred, m5ImmPred,
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defm: MemOpi_m5Pats <load, store, u6_2ExtPred, m5ImmPred,
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ADDRriU6_2, MEMOPIMM, L4_isub_memopw_io>;
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}
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@ -2832,46 +2830,46 @@ multiclass MemOpi_bitPats <PatFrag ldOp, PatFrag stOp, PatLeaf immPred,
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// mem[bhw](Rs+#u6:[012]) = [clrbit|setbit](#U5)
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let AddedComplexity = 250 in
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def : Pat<(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
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immPred:$bitend),
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(add IntRegs:$base, extPred:$offset)),
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(MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$bitend))>;
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def: Pat<(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
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immPred:$bitend),
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(add IntRegs:$base, extPred:$offset)),
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(MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$bitend))>;
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// mem[bhw](Rs+#0) = [clrbit|setbit](#U5)
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let AddedComplexity = 225 in
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def : Pat <(stOp (OpNode (ldOp (addrPred IntRegs:$addr, extPred:$offset)),
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immPred:$bitend),
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(addrPred (i32 IntRegs:$addr), extPred:$offset)),
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(MI IntRegs:$addr, extPred:$offset, (xformFunc immPred:$bitend))>;
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def: Pat<(stOp (OpNode (ldOp (addrPred IntRegs:$addr, extPred:$offset)),
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immPred:$bitend),
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(addrPred (i32 IntRegs:$addr), extPred:$offset)),
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(MI IntRegs:$addr, extPred:$offset, (xformFunc immPred:$bitend))>;
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}
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multiclass MemOpi_bitExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
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// Byte - clrbit
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defm : MemOpi_bitPats<ldOpByte, truncstorei8, Clr3ImmPred, u6ExtPred,
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defm: MemOpi_bitPats<ldOpByte, truncstorei8, Clr3ImmPred, u6ExtPred,
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ADDRriU6_0, CLRMEMIMM_BYTE, L4_iand_memopb_io, and>;
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// Byte - setbit
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defm : MemOpi_bitPats<ldOpByte, truncstorei8, Set3ImmPred, u6ExtPred,
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defm: MemOpi_bitPats<ldOpByte, truncstorei8, Set3ImmPred, u6ExtPred,
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ADDRriU6_0, SETMEMIMM_BYTE, L4_ior_memopb_io, or>;
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// Half Word - clrbit
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defm : MemOpi_bitPats<ldOpHalf, truncstorei16, Clr4ImmPred, u6_1ExtPred,
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defm: MemOpi_bitPats<ldOpHalf, truncstorei16, Clr4ImmPred, u6_1ExtPred,
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ADDRriU6_1, CLRMEMIMM_SHORT, L4_iand_memoph_io, and>;
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// Half Word - setbit
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defm : MemOpi_bitPats<ldOpHalf, truncstorei16, Set4ImmPred, u6_1ExtPred,
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defm: MemOpi_bitPats<ldOpHalf, truncstorei16, Set4ImmPred, u6_1ExtPred,
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ADDRriU6_1, SETMEMIMM_SHORT, L4_ior_memoph_io, or>;
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}
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let Predicates = [HasV4T, UseMEMOP] in {
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// mem[bh](Rs+#0) = [clrbit|setbit](#U5)
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// mem[bh](Rs+#u6:[01]) = [clrbit|setbit](#U5)
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defm : MemOpi_bitExtType<zextloadi8, zextloadi16>; // zero extend
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defm : MemOpi_bitExtType<sextloadi8, sextloadi16>; // sign extend
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defm : MemOpi_bitExtType<extloadi8, extloadi16>; // any extend
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defm: MemOpi_bitExtType<zextloadi8, zextloadi16>; // zero extend
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defm: MemOpi_bitExtType<sextloadi8, sextloadi16>; // sign extend
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defm: MemOpi_bitExtType<extloadi8, extloadi16>; // any extend
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// memw(Rs+#0) = [clrbit|setbit](#U5)
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// memw(Rs+#u6:2) = [clrbit|setbit](#U5)
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defm : MemOpi_bitPats<load, store, Clr5ImmPred, u6_2ExtPred, ADDRriU6_2,
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defm: MemOpi_bitPats<load, store, Clr5ImmPred, u6_2ExtPred, ADDRriU6_2,
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CLRMEMIMM, L4_iand_memopw_io, and>;
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defm : MemOpi_bitPats<load, store, Set5ImmPred, u6_2ExtPred, ADDRriU6_2,
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defm: MemOpi_bitPats<load, store, Set5ImmPred, u6_2ExtPred, ADDRriU6_2,
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SETMEMIMM, L4_ior_memopw_io, or>;
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}
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@ -2886,17 +2884,17 @@ multiclass MemOpr_Pats <PatFrag ldOp, PatFrag stOp, ComplexPattern addrPred,
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PatLeaf extPred, InstHexagon MI, SDNode OpNode> {
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let AddedComplexity = 141 in
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// mem[bhw](Rs+#0) [+-&|]= Rt
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def : Pat <(stOp (OpNode (ldOp (addrPred IntRegs:$addr, extPred:$offset)),
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(i32 IntRegs:$addend)),
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(addrPred (i32 IntRegs:$addr), extPred:$offset)),
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(MI IntRegs:$addr, extPred:$offset, (i32 IntRegs:$addend) )>;
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def: Pat<(stOp (OpNode (ldOp (addrPred IntRegs:$addr, extPred:$offset)),
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(i32 IntRegs:$addend)),
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(addrPred (i32 IntRegs:$addr), extPred:$offset)),
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(MI IntRegs:$addr, extPred:$offset, (i32 IntRegs:$addend) )>;
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// mem[bhw](Rs+#U6:[012]) [+-&|]= Rt
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let AddedComplexity = 150 in
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def : Pat <(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
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(i32 IntRegs:$orend)),
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(add IntRegs:$base, extPred:$offset)),
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(MI IntRegs:$base, extPred:$offset, (i32 IntRegs:$orend) )>;
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def: Pat<(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
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(i32 IntRegs:$orend)),
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(add IntRegs:$base, extPred:$offset)),
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(MI IntRegs:$base, extPred:$offset, (i32 IntRegs:$orend))>;
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}
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multiclass MemOPr_ALUOp<PatFrag ldOp, PatFrag stOp,
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@ -2904,32 +2902,32 @@ multiclass MemOPr_ALUOp<PatFrag ldOp, PatFrag stOp,
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InstHexagon addMI, InstHexagon subMI,
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InstHexagon andMI, InstHexagon orMI > {
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defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, addMI, add>;
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defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, subMI, sub>;
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defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, andMI, and>;
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defm : MemOpr_Pats <ldOp, stOp, addrPred, extPred, orMI, or>;
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defm: MemOpr_Pats <ldOp, stOp, addrPred, extPred, addMI, add>;
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defm: MemOpr_Pats <ldOp, stOp, addrPred, extPred, subMI, sub>;
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defm: MemOpr_Pats <ldOp, stOp, addrPred, extPred, andMI, and>;
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defm: MemOpr_Pats <ldOp, stOp, addrPred, extPred, orMI, or>;
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}
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multiclass MemOPr_ExtType<PatFrag ldOpByte, PatFrag ldOpHalf > {
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// Half Word
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defm : MemOPr_ALUOp <ldOpHalf, truncstorei16, ADDRriU6_1, u6_1ExtPred,
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L4_add_memoph_io, L4_sub_memoph_io,
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L4_and_memoph_io, L4_or_memoph_io>;
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defm: MemOPr_ALUOp <ldOpHalf, truncstorei16, ADDRriU6_1, u6_1ExtPred,
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L4_add_memoph_io, L4_sub_memoph_io,
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L4_and_memoph_io, L4_or_memoph_io>;
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// Byte
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defm : MemOPr_ALUOp <ldOpByte, truncstorei8, ADDRriU6_0, u6ExtPred,
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L4_add_memopb_io, L4_sub_memopb_io,
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L4_and_memopb_io, L4_or_memopb_io>;
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defm: MemOPr_ALUOp <ldOpByte, truncstorei8, ADDRriU6_0, u6ExtPred,
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L4_add_memopb_io, L4_sub_memopb_io,
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L4_and_memopb_io, L4_or_memopb_io>;
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}
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// Define 'def Pats' for MemOps with register addend.
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let Predicates = [HasV4T, UseMEMOP] in {
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// Byte, Half Word
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defm : MemOPr_ExtType<zextloadi8, zextloadi16>; // zero extend
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defm : MemOPr_ExtType<sextloadi8, sextloadi16>; // sign extend
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defm : MemOPr_ExtType<extloadi8, extloadi16>; // any extend
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defm: MemOPr_ExtType<zextloadi8, zextloadi16>; // zero extend
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defm: MemOPr_ExtType<sextloadi8, sextloadi16>; // sign extend
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defm: MemOPr_ExtType<extloadi8, extloadi16>; // any extend
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// Word
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defm : MemOPr_ALUOp <load, store, ADDRriU6_2, u6_2ExtPred, L4_add_memopw_io,
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L4_sub_memopw_io, L4_and_memopw_io, L4_or_memopw_io >;
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defm: MemOPr_ALUOp <load, store, ADDRriU6_2, u6_2ExtPred, L4_add_memopw_io,
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L4_sub_memopw_io, L4_and_memopw_io, L4_or_memopw_io>;
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}
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//===----------------------------------------------------------------------===//
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@ -3156,7 +3154,7 @@ def : Pat <(i32 (zext (i1 (setle (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
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// zext( setult ( and(Rs, 255), u8))
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// Use the isdigit transformation below
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// Generate code of the form 'mux_ii(cmpbgtu(Rdd, C-1),0,1)'
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// Generate code of the form 'C2_muxii(cmpbgtui(Rdd, C-1),0,1)'
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// for C code of the form r = ((c>='0') & (c<='9')) ? 1 : 0;.
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// The isdigit transformation relies on two 'clever' aspects:
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// 1) The data type is unsigned which allows us to eliminate a zero test after
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@ -3169,12 +3167,11 @@ def : Pat <(i32 (zext (i1 (setle (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
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// The code is transformed upstream of llvm into
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// retval = (c-48) < 10 ? 1 : 0;
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let AddedComplexity = 139 in
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def : Pat <(i32 (zext (i1 (setult (i32 (and (i32 IntRegs:$src1), 255)),
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u7StrictPosImmPred:$src2)))),
|
||||
(i32 (C2_muxii (i1 (A4_cmpbgtui (i32 IntRegs:$src1),
|
||||
(DEC_CONST_BYTE u7StrictPosImmPred:$src2))),
|
||||
0, 1))>,
|
||||
Requires<[HasV4T]>;
|
||||
def: Pat<(i32 (zext (i1 (setult (i32 (and (i32 IntRegs:$src1), 255)),
|
||||
u7StrictPosImmPred:$src2)))),
|
||||
(C2_muxii (A4_cmpbgtui IntRegs:$src1,
|
||||
(DEC_CONST_BYTE u7StrictPosImmPred:$src2)),
|
||||
0, 1)>, Requires<[HasV4T]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// XTYPE/PRED -
|
||||
@ -3620,11 +3617,12 @@ class T_LoadAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
|
||||
!if (!eq(ImmOpStr, "u16_1Imm"), 1,
|
||||
/* u16_0Imm */ 0)));
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Template class for predicated load instructions with
|
||||
// absolute addressing mode.
|
||||
//===----------------------------------------------------------------------===//
|
||||
let isPredicated = 1, hasNewValue = 1, opExtentBits = 6, opExtendable = 2 in
|
||||
let isPredicated = 1, opExtentBits = 6, opExtendable = 2 in
|
||||
class T_LoadAbs_Pred <string mnemonic, RegisterClass RC, bits<3> MajOp,
|
||||
bit isPredNot, bit isPredNew>
|
||||
: LDInst <(outs RC:$dst), (ins PredRegs:$src1, u6Ext:$absaddr),
|
||||
@ -3636,6 +3634,7 @@ class T_LoadAbs_Pred <string mnemonic, RegisterClass RC, bits<3> MajOp,
|
||||
|
||||
let isPredicatedNew = isPredNew;
|
||||
let isPredicatedFalse = isPredNot;
|
||||
let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
|
||||
|
||||
let IClass = 0b1001;
|
||||
|
||||
@ -3834,6 +3833,7 @@ let AddedComplexity = 120 in {
|
||||
def: Loadam_pat<extloadi32, i64, addrga, Zext64, L4_loadri_abs>;
|
||||
def: Loadam_pat<sextloadi32, i64, addrga, Sext64, L4_loadri_abs>;
|
||||
def: Loadam_pat<zextloadi32, i64, addrga, Zext64, L4_loadri_abs>;
|
||||
}
|
||||
|
||||
let AddedComplexity = 100 in {
|
||||
def: Loada_pat<extloadi8, i32, addrgp, L4_loadrub_abs>;
|
||||
@ -3847,7 +3847,7 @@ let AddedComplexity = 100 in {
|
||||
def: Loada_pat<load, i32, addrgp, L4_loadri_abs>;
|
||||
def: Loada_pat<load, i64, addrgp, L4_loadrd_abs>;
|
||||
}
|
||||
}
|
||||
|
||||
let AddedComplexity = 100 in {
|
||||
def: Storea_pat<truncstorei8, I32, addrgp, S2_storerbabs>;
|
||||
def: Storea_pat<truncstorei16, I32, addrgp, S2_storerhabs>;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user