6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-21 02:29:22 +00:00
Code Issues Projects Releases Wiki Activity

[Hexagon] Cleaning up definition formatting.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228593 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu 2015-02-09 19:24:44 +00:00
parent af30d1e97a
commit e17141f9f3
1 changed files with 85 additions and 85 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
lib/Target/Hexagon/HexagonInstrInfoV4.td
View File

@ -256,7 +256,6 @@ def: Pat<(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, (i32 IntRegs:$src2))),
(i32 IntRegs:$src1))), 0)))),
(C2_muxii (S2_tstbit_r IntRegs:$src1, IntRegs:$src2), 1, 0)>;
//===----------------------------------------------------------------------===//
// ALU32 -
//===----------------------------------------------------------------------===//
@ -1760,6 +1759,7 @@ def S4_parity: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
let Inst{12-8} = Rt;
let Inst{4-0} = Rd;
}
// Add and accumulate.
// Rd=add(Rs,add(Ru,#s6))
let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 6,
@ -1857,9 +1857,10 @@ def M4_xor_xacc
let IClass = 0b1100;
let Inst{27-23} = 0b10101;
let Inst{27-22} = 0b101010;
let Inst{20-16} = Rss;
let Inst{12-8} = Rtt;
let Inst{7-5} = 0b000;
let Inst{4-0} = Rxx;
}
@ -1910,7 +1911,6 @@ def S4_vrcrotate_acc
let Inst{4-0} = Rxx;
}
// Vector reduce conditional negate halfwords
let hasSideEffects = 0 in
def S2_vrcnegh
@ -2348,7 +2348,6 @@ def M4_pmpyw_acc : T_XTYPE_mpy64_acc < "pmpyw", "^", 0b001, 0b111, 0, 0, 0>;
// XTYPE/MPY -
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// ALU64/Vector compare
//===----------------------------------------------------------------------===//
@ -2745,7 +2744,7 @@ multiclass MemOpi_u5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf ExtPred,
let AddedComplexity = 180 in
def: Pat<(stOp (OpNode (ldOp IntRegs:$addr), u5ImmPred:$addend),
IntRegs:$addr),
(MI IntRegs:$addr, #0, u5ImmPred:$addend )>;
(MI IntRegs:$addr, 0, u5ImmPred:$addend)>;
let AddedComplexity = 190 in
def: Pat<(stOp (OpNode (ldOp (add IntRegs:$base, ExtPred:$offset)),
@ -2790,9 +2789,8 @@ multiclass MemOpi_m5Pats <PatFrag ldOp, PatFrag stOp, PatLeaf extPred,
PatLeaf immPred, ComplexPattern addrPred,
SDNodeXForm xformFunc, InstHexagon MI> {
let AddedComplexity = 190 in
def : Pat <(stOp (add (ldOp IntRegs:$addr), immPred:$subend),
IntRegs:$addr),
(MI IntRegs:$addr, #0, (xformFunc immPred:$subend) )>;
def: Pat<(stOp (add (ldOp IntRegs:$addr), immPred:$subend), IntRegs:$addr),
(MI IntRegs:$addr, 0, (xformFunc immPred:$subend))>;
let AddedComplexity = 195 in
def: Pat<(stOp (add (ldOp (add IntRegs:$base, extPred:$offset)),
@ -3156,7 +3154,7 @@ def : Pat <(i32 (zext (i1 (setle (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
// zext( setult ( and(Rs, 255), u8))
// Use the isdigit transformation below
// Generate code of the form 'mux_ii(cmpbgtu(Rdd, C-1),0,1)'
// Generate code of the form 'C2_muxii(cmpbgtui(Rdd, C-1),0,1)'
// for C code of the form r = ((c>='0') & (c<='9')) ? 1 : 0;.
// The isdigit transformation relies on two 'clever' aspects:
// 1) The data type is unsigned which allows us to eliminate a zero test after
@ -3171,10 +3169,9 @@ def : Pat <(i32 (zext (i1 (setle (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
let AddedComplexity = 139 in
def: Pat<(i32 (zext (i1 (setult (i32 (and (i32 IntRegs:$src1), 255)),
u7StrictPosImmPred:$src2)))),
(i32 (C2_muxii (i1 (A4_cmpbgtui (i32 IntRegs:$src1),
(DEC_CONST_BYTE u7StrictPosImmPred:$src2))),
0, 1))>,
Requires<[HasV4T]>;
(C2_muxii (A4_cmpbgtui IntRegs:$src1,
(DEC_CONST_BYTE u7StrictPosImmPred:$src2)),
0, 1)>, Requires<[HasV4T]>;
//===----------------------------------------------------------------------===//
// XTYPE/PRED -
@ -3620,11 +3617,12 @@ class T_LoadAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
!if (!eq(ImmOpStr, "u16_1Imm"), 1,
/* u16_0Imm */ 0)));
}
//===----------------------------------------------------------------------===//
// Template class for predicated load instructions with
// absolute addressing mode.
//===----------------------------------------------------------------------===//
let isPredicated = 1, hasNewValue = 1, opExtentBits = 6, opExtendable = 2 in
let isPredicated = 1, opExtentBits = 6, opExtendable = 2 in
class T_LoadAbs_Pred <string mnemonic, RegisterClass RC, bits<3> MajOp,
bit isPredNot, bit isPredNew>
: LDInst <(outs RC:$dst), (ins PredRegs:$src1, u6Ext:$absaddr),
@ -3636,6 +3634,7 @@ class T_LoadAbs_Pred <string mnemonic, RegisterClass RC, bits<3> MajOp,
let isPredicatedNew = isPredNew;
let isPredicatedFalse = isPredNot;
let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
let IClass = 0b1001;
@ -3834,6 +3833,7 @@ let AddedComplexity = 120 in {
def: Loadam_pat<extloadi32, i64, addrga, Zext64, L4_loadri_abs>;
def: Loadam_pat<sextloadi32, i64, addrga, Sext64, L4_loadri_abs>;
def: Loadam_pat<zextloadi32, i64, addrga, Zext64, L4_loadri_abs>;
}
let AddedComplexity = 100 in {
def: Loada_pat<extloadi8, i32, addrgp, L4_loadrub_abs>;
@ -3847,7 +3847,7 @@ let AddedComplexity = 100 in {
def: Loada_pat<load, i32, addrgp, L4_loadri_abs>;
def: Loada_pat<load, i64, addrgp, L4_loadrd_abs>;
}
}
let AddedComplexity = 100 in {
def: Storea_pat<truncstorei8, I32, addrgp, S2_storerbabs>;
def: Storea_pat<truncstorei16, I32, addrgp, S2_storerhabs>;