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Make sure SEXTLOAD of the specific type is supported on the target.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35289 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2007-03-23 22:13:36 +00:00
parent aa04035229
commit e177e307fc
1 changed files with 4 additions and 0 deletions
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4
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -2272,9 +2272,13 @@ SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
MVT::ValueType VT = N->getValueType(0);
MVT::ValueType EVT = N->getValueType(0);
// Special case: SIGN_EXTEND_INREG is basically truncating to EVT then
// extended to VT.
if (Opc == ISD::SIGN_EXTEND_INREG) {
ExtType = ISD::SEXTLOAD;
EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))
return SDOperand();
}
unsigned EVTBits = MVT::getSizeInBits(EVT);