mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Convert XLForm and XForm instructions over to use PPC64 when appropriate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21347 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
5035cef732
commit
e19d0b1130
@ -200,9 +200,9 @@ class DSForm_2<bits<6> opcode, bits<2> xo, bit ppc64, bit vmx,
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: DSForm_1<opcode, xo, ppc64, vmx, OL, asmstr>;
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// 1.7.6 X-Form
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class XForm_base_r3xo<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
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class XForm_base_r3xo<bits<6> opcode, bits<10> xo, bit rc,
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dag OL, string asmstr>
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: I<opcode, ppc64, vmx, OL, asmstr> {
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: I<opcode, 0, 0, OL, asmstr> {
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bits<5> RST;
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bits<5> A;
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bits<5> B;
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@ -217,9 +217,8 @@ class XForm_base_r3xo<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
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// This is the same as XForm_base_r3xo, but the first two operands are swapped
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// when code is emitted.
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class XForm_base_r3xo_swapped
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<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
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dag OL, string asmstr>
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: I<opcode, ppc64, vmx, OL, asmstr> {
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<bits<6> opcode, bits<10> xo, bit rc, dag OL, string asmstr>
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: I<opcode, 0, 0, OL, asmstr> {
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bits<5> A;
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bits<5> RST;
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bits<5> B;
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@ -232,31 +231,26 @@ class XForm_base_r3xo_swapped
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}
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class XForm_1<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
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dag OL, string asmstr>
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: XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr>;
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class XForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
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: XForm_base_r3xo<opcode, xo, 0, OL, asmstr>;
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class XForm_6<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
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dag OL, string asmstr>
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: XForm_base_r3xo_swapped<opcode, xo, rc, ppc64, vmx, OL, asmstr>;
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class XForm_6<bits<6> opcode, bits<10> xo, bit rc, dag OL, string asmstr>
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: XForm_base_r3xo_swapped<opcode, xo, rc, OL, asmstr>;
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class XForm_8<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
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dag OL, string asmstr>
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: XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr>;
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class XForm_8<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
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: XForm_base_r3xo<opcode, xo, 0, OL, asmstr>;
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class XForm_10<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
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dag OL, string asmstr>
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: XForm_base_r3xo_swapped<opcode, xo, rc, ppc64, vmx, OL, asmstr> {
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class XForm_10<bits<6> opcode, bits<10> xo, bit rc, dag OL, string asmstr>
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: XForm_base_r3xo_swapped<opcode, xo, rc, OL, asmstr> {
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}
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class XForm_11<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
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dag OL, string asmstr>
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: XForm_base_r3xo_swapped<opcode, xo, rc, ppc64, vmx, OL, asmstr> {
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class XForm_11<bits<6> opcode, bits<10> xo, bit rc, dag OL, string asmstr>
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: XForm_base_r3xo_swapped<opcode, xo, rc, OL, asmstr> {
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let B = 0;
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}
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class XForm_16<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
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dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
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class XForm_16<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
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: I<opcode, 0, 0, OL, asmstr> {
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bits<3> BF;
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bits<1> L;
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bits<5> RA;
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@ -271,14 +265,13 @@ class XForm_16<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
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let Inst{31} = 0;
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}
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class XForm_16_ext<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
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dag OL, string asmstr>
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: XForm_16<opcode, xo, ppc64, vmx, OL, asmstr> {
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let L = ppc64;
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class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
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: XForm_16<opcode, xo, OL, asmstr> {
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let L = PPC64;
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}
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class XForm_17<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
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dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
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class XForm_17<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
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: I<opcode, 0, 0, OL, asmstr> {
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bits<3> BF;
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bits<5> FRA;
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bits<5> FRB;
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@ -291,25 +284,22 @@ class XForm_17<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
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let Inst{31} = 0;
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}
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class XForm_25<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
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dag OL, string asmstr>
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: XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr> {
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class XForm_25<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
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: XForm_base_r3xo<opcode, xo, 0, OL, asmstr> {
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}
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class XForm_26<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
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dag OL, string asmstr>
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: XForm_base_r3xo<opcode, xo, rc, ppc64, vmx, OL, asmstr> {
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class XForm_26<bits<6> opcode, bits<10> xo, bit rc, dag OL, string asmstr>
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: XForm_base_r3xo<opcode, xo, rc, OL, asmstr> {
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let A = 0;
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}
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class XForm_28<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
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dag OL, string asmstr>
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: XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr> {
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class XForm_28<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
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: XForm_base_r3xo<opcode, xo, 0, OL, asmstr> {
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}
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// 1.7.7 XL-Form
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class XLForm_1<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
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dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
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class XLForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
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: I<opcode, 0, 0, OL, asmstr> {
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bits<3> CRD;
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bits<2> CRDb;
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bits<3> CRA;
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@ -327,8 +317,8 @@ class XLForm_1<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
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let Inst{31} = 0;
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}
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class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, bit ppc64, bit vmx,
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dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
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class XLForm_2<bits<6> opcode, bits<10> xo, bit lk,
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dag OL, string asmstr> : I<opcode, 0, 0, OL, asmstr> {
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bits<5> BO;
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bits<5> BI;
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bits<2> BH;
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@ -342,16 +332,15 @@ class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, bit ppc64, bit vmx,
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}
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class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo,
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bits<5> bi, bit lk, bit ppc64, bit vmx,
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dag OL, string asmstr>
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: XLForm_2<opcode, xo, lk, ppc64, vmx, OL, asmstr> {
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bits<5> bi, bit lk, dag OL, string asmstr>
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: XLForm_2<opcode, xo, lk, OL, asmstr> {
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let BO = bo;
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let BI = bi;
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let BH = 0;
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}
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class XLForm_3<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
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dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
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class XLForm_3<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
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: I<opcode, 0, 0, OL, asmstr> {
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bits<3> BF;
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bits<3> BFA;
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@ -20,8 +20,8 @@ class isVMX { bit VMX = 1; }
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let isTerminator = 1 in {
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let isReturn = 1 in
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def BLR : XLForm_2_ext<19, 16, 20, 0, 0, 0, 0, (ops), "blr">;
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def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, 0, 0, (ops), "bctr">;
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def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr">;
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def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr">;
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}
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def u5imm : Operand<i8> {
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@ -94,7 +94,7 @@ let isBranch = 1, isTerminator = 1, isCall = 1,
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CR0,CR1,CR5,CR6,CR7] in {
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// Convenient aliases for call instructions
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def CALLpcrel : IForm<18, 0, 1, 0, 0, (ops target:$func), "bl $func">;
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def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1, 0, 0, (ops), "bctrl">;
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def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1, (ops), "bctrl">;
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}
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// D-Form instructions. Most instructions that perform an operation on a
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@ -214,155 +214,149 @@ def STDU : DSForm_2<62, 1, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
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// register and another register are of this type.
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//
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let isLoad = 1 in {
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def LBZX : XForm_1<31, 87, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
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def LBZX : XForm_1<31, 87, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
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"lbzx $dst, $base, $index">;
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def LHAX : XForm_1<31, 343, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
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def LHAX : XForm_1<31, 343, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
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"lhax $dst, $base, $index">;
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def LHZX : XForm_1<31, 279, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
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def LHZX : XForm_1<31, 279, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
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"lhzx $dst, $base, $index">;
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def LWAX : XForm_1<31, 341, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
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"lwax $dst, $base, $index">;
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def LWZX : XForm_1<31, 23, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
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def LWAX : XForm_1<31, 341, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
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"lwax $dst, $base, $index">, isPPC64;
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def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
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"lwzx $dst, $base, $index">;
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def LDX : XForm_1<31, 21, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
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"ldx $dst, $base, $index">;
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def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
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"ldx $dst, $base, $index">, isPPC64;
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}
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def AND : XForm_6<31, 28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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def AND : XForm_6<31, 28, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"and $rA, $rS, $rB">;
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let Defs = [CR0] in
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def ANDo : XForm_6<31, 28, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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def ANDo : XForm_6<31, 28, 1, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"and. $rA, $rS, $rB">;
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def ANDC : XForm_6<31, 60, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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def ANDC : XForm_6<31, 60, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"andc $rA, $rS, $rB">;
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def EQV : XForm_6<31, 284, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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def EQV : XForm_6<31, 284, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"eqv $rA, $rS, $rB">;
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def NAND : XForm_6<31, 476, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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def NAND : XForm_6<31, 476, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"nand $rA, $rS, $rB">;
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def NOR : XForm_6<31, 124, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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def NOR : XForm_6<31, 124, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"nor $rA, $rS, $rB">;
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def OR : XForm_6<31, 444, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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def OR : XForm_6<31, 444, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"or $rA, $rS, $rB">;
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let Defs = [CR0] in
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def ORo : XForm_6<31, 444, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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def ORo : XForm_6<31, 444, 1, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"or. $rA, $rS, $rB">;
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def ORC : XForm_6<31, 412, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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def ORC : XForm_6<31, 412, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"orc $rA, $rS, $rB">;
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def SLD : XForm_6<31, 27, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"sld $rA, $rS, $rB">;
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def SLW : XForm_6<31, 24, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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def SLD : XForm_6<31, 27, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"sld $rA, $rS, $rB">, isPPC64;
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def SLW : XForm_6<31, 24, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"slw $rA, $rS, $rB">;
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def SRD : XForm_6<31, 539, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"srd $rA, $rS, $rB">;
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def SRW : XForm_6<31, 536, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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def SRD : XForm_6<31, 539, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"srd $rA, $rS, $rB">, isPPC64;
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def SRW : XForm_6<31, 536, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"srw $rA, $rS, $rB">;
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def SRAD : XForm_6<31, 794, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"srad $rA, $rS, $rB">;
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def SRAW : XForm_6<31, 792, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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def SRAD : XForm_6<31, 794, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"srad $rA, $rS, $rB">, isPPC64;
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def SRAW : XForm_6<31, 792, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"sraw $rA, $rS, $rB">;
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def XOR : XForm_6<31, 316, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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def XOR : XForm_6<31, 316, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
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"xor $rA, $rS, $rB">;
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let isStore = 1 in {
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def STBX : XForm_8<31, 215, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
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def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
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"stbx $rS, $rA, $rB">;
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def STHX : XForm_8<31, 407, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
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def STHX : XForm_8<31, 407, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
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"sthx $rS, $rA, $rB">;
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def STWX : XForm_8<31, 151, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
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def STWX : XForm_8<31, 151, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
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"stwx $rS, $rA, $rB">;
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def STWUX : XForm_8<31, 183, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
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def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
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"stwux $rS, $rA, $rB">;
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def STDX : XForm_8<31, 149, 1, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
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"stdx $rS, $rA, $rB">;
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def STDUX : XForm_8<31, 181, 1, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
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"stdux $rS, $rA, $rB">;
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def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
|
||||
"stdx $rS, $rA, $rB">, isPPC64;
|
||||
def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
|
||||
"stdux $rS, $rA, $rB">, isPPC64;
|
||||
}
|
||||
def SRAWI : XForm_10<31, 824, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
|
||||
def SRAWI : XForm_10<31, 824, 0, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
|
||||
"srawi $rA, $rS, $SH">;
|
||||
def CNTLZW : XForm_11<31, 26, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
|
||||
def CNTLZW : XForm_11<31, 26, 0, (ops GPRC:$rA, GPRC:$rS),
|
||||
"cntlzw $rA, $rS">;
|
||||
def EXTSB : XForm_11<31, 954, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
|
||||
def EXTSB : XForm_11<31, 954, 0, (ops GPRC:$rA, GPRC:$rS),
|
||||
"extsb $rA, $rS">;
|
||||
def EXTSH : XForm_11<31, 922, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
|
||||
def EXTSH : XForm_11<31, 922, 0, (ops GPRC:$rA, GPRC:$rS),
|
||||
"extsh $rA, $rS">;
|
||||
def EXTSW : XForm_11<31, 986, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS),
|
||||
"extsw $rA, $rS">;
|
||||
def CMP : XForm_16<31, 0, 0, 0,
|
||||
(ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
|
||||
def EXTSW : XForm_11<31, 986, 0, (ops GPRC:$rA, GPRC:$rS),
|
||||
"extsw $rA, $rS">, isPPC64;
|
||||
def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
|
||||
"cmp $crD, $long, $rA, $rB">;
|
||||
def CMPL : XForm_16<31, 32, 0, 0,
|
||||
(ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
|
||||
def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
|
||||
"cmpl $crD, $long, $rA, $rB">;
|
||||
def CMPW : XForm_16_ext<31, 0, 0, 0,
|
||||
(ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
|
||||
def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
|
||||
"cmpw $crD, $rA, $rB">;
|
||||
def CMPD : XForm_16_ext<31, 0, 1, 0,
|
||||
(ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
|
||||
"cmpd $crD, $rA, $rB">;
|
||||
def CMPLW : XForm_16_ext<31, 32, 0, 0,
|
||||
(ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
|
||||
def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
|
||||
"cmpd $crD, $rA, $rB">, isPPC64;
|
||||
def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
|
||||
"cmplw $crD, $rA, $rB">;
|
||||
def CMPLD : XForm_16_ext<31, 32, 1, 0,
|
||||
(ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
|
||||
"cmpld $crD, $rA, $rB">;
|
||||
def FCMPO : XForm_17<63, 32, 0, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
|
||||
def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
|
||||
"cmpld $crD, $rA, $rB">, isPPC64;
|
||||
def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
|
||||
"fcmpo $crD, $fA, $fB">;
|
||||
def FCMPU : XForm_17<63, 0, 0, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
|
||||
def FCMPU : XForm_17<63, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
|
||||
"fcmpu $crD, $fA, $fB">;
|
||||
let isLoad = 1 in {
|
||||
def LFSX : XForm_25<31, 535, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
|
||||
def LFSX : XForm_25<31, 535, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
|
||||
"lfsx $dst, $base, $index">;
|
||||
def LFDX : XForm_25<31, 599, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
|
||||
def LFDX : XForm_25<31, 599, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
|
||||
"lfdx $dst, $base, $index">;
|
||||
}
|
||||
def FCFID : XForm_26<63, 846, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB),
|
||||
"fcfid $frD, $frB">;
|
||||
def FCTIDZ : XForm_26<63, 815, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB),
|
||||
"fctidz $frD, $frB">;
|
||||
def FCTIWZ : XForm_26<63, 15, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
|
||||
def FCFID : XForm_26<63, 846, 0, (ops FPRC:$frD, FPRC:$frB),
|
||||
"fcfid $frD, $frB">, isPPC64;
|
||||
def FCTIDZ : XForm_26<63, 815, 0, (ops FPRC:$frD, FPRC:$frB),
|
||||
"fctidz $frD, $frB">, isPPC64;
|
||||
def FCTIWZ : XForm_26<63, 15, 0, (ops FPRC:$frD, FPRC:$frB),
|
||||
"fctiwz $frD, $frB">;
|
||||
def FABS : XForm_26<63, 264, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
|
||||
def FABS : XForm_26<63, 264, 0, (ops FPRC:$frD, FPRC:$frB),
|
||||
"fabs $frD, $frB">;
|
||||
def FMR : XForm_26<63, 72, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
|
||||
def FMR : XForm_26<63, 72, 0, (ops FPRC:$frD, FPRC:$frB),
|
||||
"fmr $frD, $frB">;
|
||||
def FNABS : XForm_26<63, 136, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
|
||||
def FNABS : XForm_26<63, 136, 0, (ops FPRC:$frD, FPRC:$frB),
|
||||
"fnabs $frD, $frB">;
|
||||
def FNEG : XForm_26<63, 40, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
|
||||
def FNEG : XForm_26<63, 40, 0, (ops FPRC:$frD, FPRC:$frB),
|
||||
"fneg $frD, $frB">;
|
||||
def FRSP : XForm_26<63, 12, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
|
||||
def FRSP : XForm_26<63, 12, 0, (ops FPRC:$frD, FPRC:$frB),
|
||||
"frsp $frD, $frB">;
|
||||
let isStore = 1 in {
|
||||
def STFSX : XForm_28<31, 663, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
|
||||
def STFSX : XForm_28<31, 663, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
|
||||
"stfsx $frS, $rA, $rB">;
|
||||
def STFDX : XForm_28<31, 727, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
|
||||
def STFDX : XForm_28<31, 727, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
|
||||
"stfdx $frS, $rA, $rB">;
|
||||
}
|
||||
|
||||
// XL-Form instructions. condition register logical ops.
|
||||
//
|
||||
def CRAND : XLForm_1<19, 257, 0, 0, (ops CRRC:$D, crbit:$Db,
|
||||
def CRAND : XLForm_1<19, 257, (ops CRRC:$D, crbit:$Db,
|
||||
CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
|
||||
"crand $Db, $Ab, $Bb">;
|
||||
def CRANDC : XLForm_1<19, 129, 0, 0, (ops CRRC:$D, crbit:$Db,
|
||||
def CRANDC : XLForm_1<19, 129, (ops CRRC:$D, crbit:$Db,
|
||||
CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
|
||||
"crandc $Db, $Ab, $Bb">;
|
||||
def CREQV : XLForm_1<19, 289, 0, 0, (ops CRRC:$D, crbit:$Db,
|
||||
def CREQV : XLForm_1<19, 289, (ops CRRC:$D, crbit:$Db,
|
||||
CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
|
||||
"creqv $Db, $Ab, $Bb">;
|
||||
def CRNAND : XLForm_1<19, 225, 0, 0, (ops CRRC:$D, crbit:$Db,
|
||||
def CRNAND : XLForm_1<19, 225, (ops CRRC:$D, crbit:$Db,
|
||||
CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
|
||||
"crnand $Db, $Ab, $Bb">;
|
||||
def CRNOR : XLForm_1<19, 33, 0, 0, (ops CRRC:$D, crbit:$Db,
|
||||
def CRNOR : XLForm_1<19, 33, (ops CRRC:$D, crbit:$Db,
|
||||
CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
|
||||
"crnor $Db, $Ab, $Bb">;
|
||||
def CROR : XLForm_1<19, 449, 0, 0, (ops CRRC:$D, crbit:$Db,
|
||||
def CROR : XLForm_1<19, 449, (ops CRRC:$D, crbit:$Db,
|
||||
CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
|
||||
"cror $Db, $Ab, $Bb">;
|
||||
def CRORC : XLForm_1<19, 417, 0, 0, (ops CRRC:$D, crbit:$Db,
|
||||
def CRORC : XLForm_1<19, 417, (ops CRRC:$D, crbit:$Db,
|
||||
CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
|
||||
"crorc $Db, $Ab, $Bb">;
|
||||
def CRXOR : XLForm_1<19, 193, 0, 0, (ops CRRC:$D, crbit:$Db,
|
||||
def CRXOR : XLForm_1<19, 193, (ops CRRC:$D, crbit:$Db,
|
||||
CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
|
||||
"crxor $Db, $Ab, $Bb">;
|
||||
def MCRF : XLForm_3<19, 0, 0, 0, (ops CRRC:$BF, CRRC:$BFA),
|
||||
def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
|
||||
"mcrf $BF, $BFA">;
|
||||
|
||||
// XFX-Form instructions. Instructions that deal with SPRs
|
||||
|
||||
Loading…
Reference in New Issue
Block a user