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https://github.com/c64scene-ar/llvm-6502.git
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AVX-512: added VPERM2D VPERM2Q VPERM2PS VPERM2PD instructions,
they give better sequences than VPERMI git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199893 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky
parent
1334acd8c6
commit
e1a621d84f
@ -7588,8 +7588,8 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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// Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
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return DAG.getNode(X86ISD::VPERMV, dl, VT,
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DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
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return DAG.getNode(X86ISD::VPERMV3, dl, VT,
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DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1, V2);
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return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
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DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
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}
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//===--------------------------------------------------------------------===//
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@ -14023,6 +14023,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
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case X86ISD::VPERMV: return "X86ISD::VPERMV";
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case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
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case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
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case X86ISD::VPERMI: return "X86ISD::VPERMI";
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case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
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case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
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@ -339,6 +339,7 @@ namespace llvm {
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VPERMILP,
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VPERMV,
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VPERMV3,
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VPERMIV3,
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VPERMI,
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VPERM2X128,
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VBROADCAST,
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@ -584,14 +584,14 @@ defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
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// -- VPERM2I - 3 source operands form --
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multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
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PatFrag mem_frag, X86MemOperand x86memop,
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ValueType OpVT> {
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SDNode OpNode, ValueType OpVT> {
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let Constraints = "$src1 = $dst" in {
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def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, RC:$src3),
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!strconcat(OpcodeStr,
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" \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set RC:$dst,
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(OpVT (X86VPermv3 RC:$src1, RC:$src2, RC:$src3)))]>,
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(OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
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EVEX_4V;
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def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
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@ -599,19 +599,27 @@ let Constraints = "$src1 = $dst" in {
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!strconcat(OpcodeStr,
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" \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set RC:$dst,
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(OpVT (X86VPermv3 RC:$src1, RC:$src2,
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(OpVT (OpNode RC:$src1, RC:$src2,
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(mem_frag addr:$src3))))]>, EVEX_4V;
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}
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}
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defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
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v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
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X86VPermiv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
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v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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X86VPermiv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
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v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
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X86VPermiv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
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v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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X86VPermiv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPERM2D : avx512_perm_3src<0x7E, "vperm2d", VR512, memopv16i32, i512mem,
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X86VPermv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPERM2Q : avx512_perm_3src<0x7E, "vperm2q", VR512, memopv8i64, i512mem,
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X86VPermv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VPERM2PS : avx512_perm_3src<0x7F, "vperm2ps", VR512, memopv16f32, i512mem,
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X86VPermv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPERM2PD : avx512_perm_3src<0x7F, "vperm2pd", VR512, memopv8f64, i512mem,
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X86VPermv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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//===----------------------------------------------------------------------===//
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// AVX-512 - BLEND using mask
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//
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@ -822,8 +830,8 @@ multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
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[], d>, EVEX_B;
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def rmi : AVX512PIi8<0xC2, MRMSrcMem,
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(outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
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!strconcat("vcmp", suffix,
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"\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
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!strconcat("vcmp${cc}", suffix,
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" \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
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[(set KRC:$dst,
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(X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
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@ -1200,12 +1208,12 @@ def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
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multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
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X86MemOperand x86memop, PatFrag ld_frag,
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string asm, Domain d> {
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string asm, Domain d, bit IsReMaterializable = 1> {
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let hasSideEffects = 0 in
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def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
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!strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
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EVEX;
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let canFoldAsLoad = 1 in
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let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
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def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
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!strconcat(asm, " \t{$src, $dst|$dst, $src}"),
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[(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
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@ -1234,7 +1242,7 @@ defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
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"vmovups", SSEPackedSingle>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
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"vmovupd", SSEPackedDouble>,
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"vmovupd", SSEPackedDouble, 0>,
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PD, EVEX_V512, VEX_W,
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EVEX_CD8<64, CD8VF>;
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def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
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@ -224,6 +224,7 @@ def X86VPermilp : SDNode<"X86ISD::VPERMILP", SDTShuff2OpI>;
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def X86VPermv : SDNode<"X86ISD::VPERMV", SDTShuff2Op>;
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def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>;
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def X86VPermv3 : SDNode<"X86ISD::VPERMV3", SDTShuff3Op>;
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def X86VPermiv3 : SDNode<"X86ISD::VPERMIV3", SDTShuff3Op>;
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def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
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@ -1540,8 +1540,8 @@ static bool isFrameLoadOpcode(int Opcode) {
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case X86::VMOVDQAYrm:
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case X86::MMX_MOVD64rm:
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case X86::MMX_MOVQ64rm:
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case X86::VMOVDQA32rm:
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case X86::VMOVDQA64rm:
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case X86::VMOVAPSZrm:
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case X86::VMOVUPSZrm:
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return true;
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}
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}
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@ -1567,6 +1567,8 @@ static bool isFrameStoreOpcode(int Opcode) {
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case X86::VMOVAPSYmr:
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case X86::VMOVAPDYmr:
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case X86::VMOVDQAYmr:
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case X86::VMOVUPSZmr:
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case X86::VMOVAPSZmr:
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case X86::MMX_MOVD64mr:
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case X86::MMX_MOVQ64mr:
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case X86::MMX_MOVNTQmr:
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@ -49,7 +49,7 @@ define <8 x double> @test4(<8 x double> %a) nounwind {
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}
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; CHECK-LABEL: test5:
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; CHECK: vpermi2pd
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; CHECK: vperm2pd
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; CHECK: ret
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define <8 x double> @test5(<8 x double> %a, <8 x double> %b) nounwind {
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%c = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 2, i32 8, i32 0, i32 1, i32 6, i32 10, i32 4, i32 5>
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@ -65,7 +65,7 @@ define <8 x i64> @test6(<8 x i64> %a) nounwind {
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}
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; CHECK-LABEL: test7:
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; CHECK: vpermi2q
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; CHECK: vperm2q
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; CHECK: ret
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define <8 x i64> @test7(<8 x i64> %a, <8 x i64> %b) nounwind {
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%c = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 2, i32 8, i32 0, i32 1, i32 6, i32 10, i32 4, i32 5>
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@ -73,7 +73,7 @@ define <8 x i64> @test7(<8 x i64> %a, <8 x i64> %b) nounwind {
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}
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; CHECK-LABEL: test8:
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; CHECK: vpermi2d
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; CHECK: vperm2d
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; CHECK: ret
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define <16 x i32> @test8(<16 x i32> %a, <16 x i32> %b) nounwind {
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%c = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32> <i32 15, i32 31, i32 14, i32 22, i32 13, i32 29, i32 4, i32 28, i32 11, i32 27, i32 10, i32 26, i32 9, i32 25, i32 8, i32 24>
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@ -81,7 +81,7 @@ define <16 x i32> @test8(<16 x i32> %a, <16 x i32> %b) nounwind {
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}
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; CHECK-LABEL: test9:
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; CHECK: vpermi2ps
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; CHECK: vperm2ps
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; CHECK: ret
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define <16 x float> @test9(<16 x float> %a, <16 x float> %b) nounwind {
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%c = shufflevector <16 x float> %a, <16 x float> %b, <16 x i32> <i32 15, i32 31, i32 14, i32 22, i32 13, i32 29, i32 4, i32 28, i32 11, i32 27, i32 10, i32 26, i32 9, i32 25, i32 8, i32 24>
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@ -89,7 +89,7 @@ define <16 x float> @test9(<16 x float> %a, <16 x float> %b) nounwind {
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}
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; CHECK-LABEL: test10:
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; CHECK: vpermi2ps (
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; CHECK: vperm2ps (
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; CHECK: ret
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define <16 x float> @test10(<16 x float> %a, <16 x float>* %b) nounwind {
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%c = load <16 x float>* %b
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@ -98,7 +98,7 @@ define <16 x float> @test10(<16 x float> %a, <16 x float>* %b) nounwind {
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}
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; CHECK-LABEL: test11:
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; CHECK: vpermi2d (
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; CHECK: vperm2d
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; CHECK: ret
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define <16 x i32> @test11(<16 x i32> %a, <16 x i32>* %b) nounwind {
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%c = load <16 x i32>* %b
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@ -202,7 +202,7 @@ define <16 x float> @test23(<16 x float> %a, <16 x float> %c) {
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}
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; CHECK-LABEL: @test24
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; CHECK: vpermi2d
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; CHECK: vperm2d
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; CHECK: ret
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define <16 x i32> @test24(<16 x i32> %a, <16 x i32> %b) nounwind {
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%c = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 19, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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