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Revert r164061-r164067. Most of the new subtarget emitter.

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I have to work out the Target/CodeGen header dependencies
before putting this back.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164072 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick
2012-09-17 23:00:42 +00:00
parent 419e5b9d4f
commit e1b5328717
13 changed files with 64 additions and 356 deletions
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14
lib/CodeGen/TargetInstrInfoImpl.cpp
View File

@@ -606,13 +606,13 @@ getOperandLatency(const InstrItineraryData *ItinData,
/// If we can determine the operand latency from the def only, without itinerary
/// lookup, do so. Otherwise return -1.
int TargetInstrInfo::computeDefOperandLatency(
const InstrItineraryData *ItinData,
const MachineInstr *DefMI, bool FindMin) const {
static int computeDefOperandLatency(
const TargetInstrInfo *TII, const InstrItineraryData *ItinData,
const MachineInstr *DefMI, bool FindMin) {
// Let the target hook getInstrLatency handle missing itineraries.
if (!ItinData)
return getInstrLatency(ItinData, DefMI);
return TII->getInstrLatency(ItinData, DefMI);
// Return a latency based on the itinerary properties and defining instruction
// if possible. Some common subtargets don't require per-operand latency,
@@ -621,7 +621,7 @@ int TargetInstrInfo::computeDefOperandLatency(
// If MinLatency is valid, call getInstrLatency. This uses Stage latency if
// it exists before defaulting to MinLatency.
if (ItinData->SchedModel->MinLatency >= 0)
return getInstrLatency(ItinData, DefMI);
return TII->getInstrLatency(ItinData, DefMI);
// If MinLatency is invalid, OperandLatency is interpreted as MinLatency.
// For empty itineraries, short-cirtuit the check and default to one cycle.
@@ -629,7 +629,7 @@ int TargetInstrInfo::computeDefOperandLatency(
return 1;
}
else if(ItinData->isEmpty())
return defaultDefLatency(ItinData->SchedModel, DefMI);
return TII->defaultDefLatency(ItinData->SchedModel, DefMI);
// ...operand lookup required
return -1;
@@ -652,7 +652,7 @@ computeOperandLatency(const InstrItineraryData *ItinData,
const MachineInstr *UseMI, unsigned UseIdx,
bool FindMin) const {
int DefLatency = computeDefOperandLatency(ItinData, DefMI, FindMin);
int DefLatency = computeDefOperandLatency(this, ItinData, DefMI, FindMin);
if (DefLatency >= 0)
return DefLatency;

140
lib/CodeGen/TargetSchedule.cpp
View File

@@ -14,7 +14,6 @@
#include "llvm/CodeGen/TargetSchedule.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include "llvm/Support/CommandLine.h"
@@ -23,9 +22,6 @@ using namespace llvm;
static cl::opt<bool> EnableSchedModel("schedmodel", cl::Hidden, cl::init(false),
cl::desc("Use TargetSchedModel for latency lookup"));
static cl::opt<bool> EnableSchedItins("scheditins", cl::Hidden, cl::init(true),
cl::desc("Use InstrItineraryData for latency lookup"));
void TargetSchedModel::init(const MCSchedModel &sm,
const TargetSubtargetInfo *sti,
const TargetInstrInfo *tii) {
@@ -34,139 +30,3 @@ void TargetSchedModel::init(const MCSchedModel &sm,
TII = tii;
STI->initInstrItins(InstrItins);
}
/// If we can determine the operand latency from the def only, without machine
/// model or itinerary lookup, do so. Otherwise return -1.
int TargetSchedModel::getDefLatency(const MachineInstr *DefMI,
bool FindMin) const {
// Return a latency based on the itinerary properties and defining instruction
// if possible. Some common subtargets don't require per-operand latency,
// especially for minimum latencies.
if (FindMin) {
// If MinLatency is invalid, then use the itinerary for MinLatency. If no
// itinerary exists either, then use single cycle latency.
if (SchedModel.MinLatency < 0
&& !(EnableSchedItins && hasInstrItineraries())) {
return 1;
}
return SchedModel.MinLatency;
}
else if (!(EnableSchedModel && hasInstrSchedModel())
&& !(EnableSchedItins && hasInstrItineraries())) {
return TII->defaultDefLatency(&SchedModel, DefMI);
}
// ...operand lookup required
return -1;
}
/// Return the MCSchedClassDesc for this instruction. Some SchedClasses require
/// evaluation of predicates that depend on instruction operands or flags.
const MCSchedClassDesc *TargetSchedModel::
resolveSchedClass(const MachineInstr *MI) const {
// Get the definition's scheduling class descriptor from this machine model.
unsigned SchedClass = MI->getDesc().getSchedClass();
const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass);
#ifndef NDEBUG
unsigned NIter = 0;
#endif
while (SCDesc->isVariant()) {
assert(++NIter < 6 && "Variants are nested deeper than the magic number");
SchedClass = STI->resolveSchedClass(SchedClass, MI, this);
SCDesc = SchedModel.getSchedClassDesc(SchedClass);
}
return SCDesc;
}
/// Find the def index of this operand. This index maps to the machine model and
/// is independent of use operands. Def operands may be reordered with uses or
/// merged with uses without affecting the def index (e.g. before/after
/// regalloc). However, an instruction's def operands must never be reordered
/// with respect to each other.
static unsigned findDefIdx(const MachineInstr *MI, unsigned DefOperIdx) {
unsigned DefIdx = 0;
for (unsigned i = 0; i != DefOperIdx; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (MO.isReg() && MO.isDef())
++DefIdx;
}
return DefIdx;
}
/// Find the use index of this operand. This is independent of the instruction's
/// def operands.
static unsigned findUseIdx(const MachineInstr *MI, unsigned UseOperIdx) {
unsigned UseIdx = 0;
for (unsigned i = 0; i != UseOperIdx; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (MO.isReg() && MO.isUse())
++UseIdx;
}
return UseIdx;
}
// Top-level API for clients that know the operand indices.
unsigned TargetSchedModel::computeOperandLatency(
const MachineInstr *DefMI, unsigned DefOperIdx,
const MachineInstr *UseMI, unsigned UseOperIdx,
bool FindMin) const {
int DefLatency = getDefLatency(DefMI, FindMin);
if (DefLatency >= 0)
return DefLatency;
if (!FindMin && EnableSchedModel && hasInstrSchedModel()) {
const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
if (DefIdx < SCDesc->NumWriteLatencyEntries) {
// Lookup the definition's write latency in SubtargetInfo.
const MCWriteLatencyEntry *WLEntry =
STI->getWriteLatencyEntry(SCDesc, DefIdx);
unsigned WriteID = WLEntry->WriteResourceID;
unsigned Latency = WLEntry->Cycles;
if (!UseMI)
return Latency;
// Lookup the use's latency adjustment in SubtargetInfo.
const MCSchedClassDesc *UseDesc = resolveSchedClass(UseMI);
if (UseDesc->NumReadAdvanceEntries == 0)
return Latency;
unsigned UseIdx = findUseIdx(UseMI, UseOperIdx);
return Latency - STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID);
}
// If DefIdx does not exist in the model (e.g. implicit defs), then return
// unit latency (defaultDefLatency may be too conservative).
// TODO: For unknown defs, we may want to use the subtarget's model
// for WAW latency here instead of 1 cycle.
assert((!SCDesc->isValid() || DefMI->getOperand(DefOperIdx).isImplicit()) &&
"DefIdx exceeds machine model def operand list");
return 1;
}
assert(EnableSchedItins && hasInstrItineraries() &&
"operand latency requires itinerary");
int OperLatency = 0;
if (UseMI) {
OperLatency =
TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx, UseMI, UseOperIdx);
}
else {
unsigned DefClass = DefMI->getDesc().getSchedClass();
OperLatency = InstrItins.getOperandCycle(DefClass, DefOperIdx);
}
if (OperLatency >= 0)
return OperLatency;
// No operand latency was found.
unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI);
// Expected latency is the max of the stage latency and itinerary props.
if (!FindMin)
InstrLatency = std::max(InstrLatency,
TII->defaultDefLatency(&SchedModel, DefMI));
return InstrLatency;
}