6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-16 11:30:51 +00:00
Code Issues Projects Releases Wiki Activity

More SPU v2f32 stuff added: insertelement and shuffle.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110038 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kalle Raiskila 2010-08-02 11:22:10 +00:00
parent c9fda996fc
commit e1c9159f63
3 changed files with 19 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
lib/Target/CellSPU/SPUISelLowering.cpp
View File

@ -1624,6 +1624,7 @@ LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
SDValue T = DAG.getConstant(unsigned(SplatBits), VT.getVectorElementType()); SDValue T = DAG.getConstant(unsigned(SplatBits), VT.getVectorElementType());
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, T, T, T, T); return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, T, T, T, T);
} }
case MVT::v2f32:
case MVT::v2i32: { case MVT::v2i32: {
return SDValue(); return SDValue();
} }

8
lib/Target/CellSPU/SPUInstrInfo.td
View File

@ -1584,6 +1584,9 @@ def : Pat<(v2i64 (SPUprefslot2vec R64C:$rA)),
def : Pat<(v4f32 (SPUprefslot2vec R32FP:$rA)), def : Pat<(v4f32 (SPUprefslot2vec R32FP:$rA)),
(ORv4f32_f32 R32FP:$rA)>; (ORv4f32_f32 R32FP:$rA)>;
def : Pat<(v2f32 (SPUprefslot2vec R32FP:$rA)),
(ORv4f32_f32 R32FP:$rA)>;
def : Pat<(v2f64 (SPUprefslot2vec R64FP:$rA)), def : Pat<(v2f64 (SPUprefslot2vec R64FP:$rA)),
(ORv2f64_f64 R64FP:$rA)>; (ORv2f64_f64 R64FP:$rA)>;
@ -1608,6 +1611,9 @@ def : Pat<(SPUvec2prefslot (v2i64 VECREG:$rA)),
def : Pat<(SPUvec2prefslot (v4f32 VECREG:$rA)), def : Pat<(SPUvec2prefslot (v4f32 VECREG:$rA)),
(ORf32_v4f32 VECREG:$rA)>; (ORf32_v4f32 VECREG:$rA)>;
def : Pat<(SPUvec2prefslot (v2f32 VECREG:$rA)),
(ORf32_v4f32 VECREG:$rA)>;
def : Pat<(SPUvec2prefslot (v2f64 VECREG:$rA)), def : Pat<(SPUvec2prefslot (v2f64 VECREG:$rA)),
(ORf64_v2f64 VECREG:$rA)>; (ORf64_v2f64 VECREG:$rA)>;
@ -2150,6 +2156,8 @@ multiclass ShuffleBytes
def v4f32 : SHUFBVecInst<v4f32, v16i8>; def v4f32 : SHUFBVecInst<v4f32, v16i8>;
def v4f32_m32 : SHUFBVecInst<v4f32, v4i32>; def v4f32_m32 : SHUFBVecInst<v4f32, v4i32>;
def v2f32 : SHUFBVecInst<v2f32, v16i8>;
def v2f32_m32 : SHUFBVecInst<v2f32, v4i32>;
def v2f64 : SHUFBVecInst<v2f64, v16i8>; def v2f64 : SHUFBVecInst<v2f64, v16i8>;
def v2f64_m32 : SHUFBVecInst<v2f64, v4i32>; def v2f64_m32 : SHUFBVecInst<v2f64, v4i32>;

10
test/CodeGen/CellSPU/v2f32.ll
View File

@ -33,3 +33,13 @@ define %vec @test_mul(%vec %param)
ret %vec %1 ret %vec %1
} }
define %vec @test_splat(float %param ) {
;CHECK: lqa
;CHECK: shufb
%sv = insertelement <1 x float> undef, float %param, i32 0
%rv = shufflevector <1 x float> %sv, <1 x float> undef, <2 x i32> zeroinitializer
;CHECK: bi $lr
ret %vec %rv
}