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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42622 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2007-10-05 01:33:45 +00:00
parent 66f0f64082
commit e203ae9971
2 changed files with 72 additions and 0 deletions
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62
lib/Target/IA64/IA64RegisterInfo.cpp
View File

@ -60,6 +60,38 @@ void IA64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
"sorry, I don't know how to store this sort of reg in the stack\n");
}
void IA64RegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
SmallVector<MachineOperand,4> Addr,
const TargetRegisterClass *RC,
SmallVector<MachineInstr*, 4> &NewMIs) const {
unsigned Opc = 0;
if (RC == IA64::FPRegisterClass) {
Opc = IA64::STF8;
} else if (RC == IA64::GRRegisterClass) {
Opc = IA64::ST8;
} else if (RC == IA64::PRRegisterClass) {
Opc = IA64::ST1;
} else {
assert(0 &&
"sorry, I don't know how to store this sort of reg\n");
}
MachineInstrBuilder MIB = BuildMI(TII.get(Opc));
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
if (MO.isRegister())
MIB.addReg(MO.getReg());
else if (MO.isImmediate())
MIB.addImm(MO.getImmedValue());
else
MIB.addFrameIndex(MO.getFrameIndex());
}
MIB.addReg(SrcReg, false, false, true);
NewMIs.push_back(MIB);
return;
}
void IA64RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIdx,
@ -80,6 +112,36 @@ void IA64RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
"sorry, I don't know how to load this sort of reg from the stack\n");
}
void IA64RegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
SmallVector<MachineOperand,4> Addr,
const TargetRegisterClass *RC,
SmallVector<MachineInstr*, 4> &NewMIs) const {
unsigned Opc = 0;
if (RC == IA64::FPRegisterClass) {
Opc = IA64::LDF8;
} else if (RC == IA64::GRRegisterClass) {
Opc = IA64::LD8;
} else if (RC == IA64::PRRegisterClass) {
Opc = IA64::LD1;
} else {
assert(0 &&
"sorry, I don't know how to store this sort of reg\n");
}
MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
if (MO.isRegister())
MIB.addReg(MO.getReg());
else if (MO.isImmediate())
MIB.addImm(MO.getImmedValue());
else
MIB.addFrameIndex(MO.getFrameIndex());
}
NewMIs.push_back(MIB);
return;
}
void IA64RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,

10
lib/Target/IA64/IA64RegisterInfo.h
View File

@ -34,11 +34,21 @@ struct IA64RegisterInfo : public IA64GenRegisterInfo {
unsigned SrcReg, int FrameIndex,
const TargetRegisterClass *RC) const;
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
SmallVector<MachineOperand,4> Addr,
const TargetRegisterClass *RC,
SmallVector<MachineInstr*, 4> &NewMIs) const;
void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC) const;
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
SmallVector<MachineOperand,4> Addr,
const TargetRegisterClass *RC,
SmallVector<MachineInstr*, 4> &NewMIs) const;
void copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,