diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index 270fac959e1..06af4b3d2e0 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -121,7 +121,8 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) { } } if (!MemOpChains.empty()) - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOpChains); + Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, + &MemOpChains[0], MemOpChains.size()); // Build a sequence of copy-to-reg nodes chained together with token chain // and flag operands which copy the outgoing args into the appropriate regs. diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index d767190ab11..9c44f5555fe 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -261,7 +261,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, } //Set up a token factor with all the stack traffic - Root = DAG.getNode(ISD::TokenFactor, MVT::Other, LS); + Root = DAG.getNode(ISD::TokenFactor, MVT::Other, &LS[0], LS.size()); } ArgValues.push_back(Root); diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp index 4cc85fb1e88..d4bc5d0ce2b 100644 --- a/lib/Target/IA64/IA64ISelLowering.cpp +++ b/lib/Target/IA64/IA64ISelLowering.cpp @@ -396,7 +396,7 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain, // Emit all stores, make sure they occur before any copies into physregs. if (!Stores.empty()) - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); + Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size()); static const unsigned IntArgRegs[] = { IA64::out0, IA64::out1, IA64::out2, IA64::out3, diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index b9ddb3005f2..9e54ada35c0 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -895,7 +895,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, // If this function is vararg, store any remaining integer argument regs // to their spots on the stack so that they may be loaded by deferencing the // result of va_next. - std::vector MemOps; + SmallVector MemOps; for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); MF.addLiveIn(GPR[GPR_idx], VReg); @@ -908,7 +908,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); } if (!MemOps.empty()) - Root = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps); + Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size()); } ArgValues.push_back(Root); @@ -1011,7 +1011,7 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) { const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; std::vector > RegsToPass; - std::vector MemOpChains; + SmallVector MemOpChains; for (unsigned i = 0; i != NumOps; ++i) { SDOperand Arg = Op.getOperand(5+2*i); @@ -1096,7 +1096,8 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) { } } if (!MemOpChains.empty()) - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOpChains); + Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, + &MemOpChains[0], MemOpChains.size()); // Build a sequence of copy-to-reg nodes chained together with token chain // and flag operands which copy the outgoing args into the appropriate regs. @@ -1609,8 +1610,10 @@ static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT, // Build a canonical splat for this value. SDOperand Elt = DAG.getConstant(Val, MVT::getVectorBaseType(CanonicalVT)); - std::vector Ops(MVT::getVectorNumElements(CanonicalVT), Elt); - SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, Ops); + SmallVector Ops; + Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt); + SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, + &Ops[0], Ops.size()); return DAG.getNode(ISD::BIT_CONVERT, VT, Res); } @@ -1643,11 +1646,11 @@ static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt, LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS); RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS); - std::vector Ops; + SDOperand Ops[16]; for (unsigned i = 0; i != 16; ++i) - Ops.push_back(DAG.getConstant(i+Amt, MVT::i32)); + Ops[i] = DAG.getConstant(i+Amt, MVT::i32); SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS, - DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops)); + DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16)); return DAG.getNode(ISD::BIT_CONVERT, VT, T); } @@ -1879,12 +1882,12 @@ static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS, case OP_VSLDOI12: return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG); } - std::vector Ops; + SDOperand Ops[16]; for (unsigned i = 0; i != 16; ++i) - Ops.push_back(DAG.getConstant(ShufIdxs[i], MVT::i32)); + Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32); return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS, - DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops)); + DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); } /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this @@ -1992,7 +1995,7 @@ static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { MVT::ValueType EltVT = MVT::getVectorBaseType(V1.getValueType()); unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8; - std::vector ResultMask; + SmallVector ResultMask; for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) { unsigned SrcElt; if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF) @@ -2005,7 +2008,8 @@ static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { MVT::i8)); } - SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, ResultMask); + SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, + &ResultMask[0], ResultMask.size()); return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask); } @@ -2180,14 +2184,13 @@ static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) { OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts); // Merge the results together. - std::vector Ops; + SDOperand Ops[16]; for (unsigned i = 0; i != 8; ++i) { - Ops.push_back(DAG.getConstant(2*i+1, MVT::i8)); - Ops.push_back(DAG.getConstant(2*i+1+16, MVT::i8)); + Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8); + Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8); } - return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts, - DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops)); + DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); } else { assert(0 && "Unknown mul to lower!"); abort(); diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 69b3dea0302..4f1feb1c615 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -2365,7 +2365,8 @@ X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT)); else MaskVec.push_back(DAG.getConstant(i+NumElems, EVT)); - SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec); + SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, + &MaskVec[0], MaskVec.size()); return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask); } @@ -2501,14 +2502,15 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { MaskVec.push_back(PermMask.getOperand(i)); for (unsigned i = 4; i != 8; ++i) MaskVec.push_back(DAG.getConstant(i, BaseVT)); - SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec); + SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, + &MaskVec[0], MaskVec.size()); V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask); MaskVec.clear(); for (unsigned i = 0; i != 4; ++i) MaskVec.push_back(DAG.getConstant(i, BaseVT)); for (unsigned i = 4; i != 8; ++i) MaskVec.push_back(PermMask.getOperand(i)); - Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec); + Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0],MaskVec.size()); return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask); } } else { @@ -2558,7 +2560,8 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { } if (NumLo <= 2 && NumHi <= 2) { V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, - DAG.getNode(ISD::BUILD_VECTOR, MaskVT, Mask1)); + DAG.getNode(ISD::BUILD_VECTOR, MaskVT, + &Mask1[0], Mask1.size())); for (unsigned i = 0; i != NumElems; ++i) { if (Locs[i].first == -1) continue; @@ -2570,7 +2573,8 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { } return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, - DAG.getNode(ISD::BUILD_VECTOR, MaskVT, Mask2)); + DAG.getNode(ISD::BUILD_VECTOR, MaskVT, + &Mask2[0], Mask2.size())); } // Break it into (shuffle shuffle_hi, shuffle_lo). @@ -2604,10 +2608,12 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { SDOperand LoShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, - DAG.getNode(ISD::BUILD_VECTOR, MaskVT, LoMask)); + DAG.getNode(ISD::BUILD_VECTOR, MaskVT, + &LoMask[0], LoMask.size())); SDOperand HiShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, - DAG.getNode(ISD::BUILD_VECTOR, MaskVT, HiMask)); + DAG.getNode(ISD::BUILD_VECTOR, MaskVT, + &HiMask[0], HiMask.size())); std::vector MaskOps; for (unsigned i = 0; i != NumElems; ++i) { if (Locs[i].first == -1) { @@ -2618,7 +2624,8 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { } } return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle, - DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskOps)); + DAG.getNode(ISD::BUILD_VECTOR, MaskVT, + &MaskOps[0], MaskOps.size())); } return SDOperand(); @@ -2651,7 +2658,8 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT))); IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT))); IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT))); - SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, IdxVec); + SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, + &IdxVec[0], IdxVec.size()); Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(), Vec, Vec, Mask); return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec, @@ -2669,7 +2677,8 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { std::vector IdxVec; IdxVec.push_back(DAG.getConstant(1, MVT::getVectorBaseType(MaskVT))); IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT))); - SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, IdxVec); + SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, + &IdxVec[0], IdxVec.size()); Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(), Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask); return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec, @@ -2706,7 +2715,8 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { for (unsigned i = 1; i <= 3; ++i) MaskVec.push_back(DAG.getConstant(i, BaseVT)); return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, N0, N1, - DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec)); + DAG.getNode(ISD::BUILD_VECTOR, MaskVT, + &MaskVec[0], MaskVec.size())); } else { // Use two pinsrw instructions to insert a 32 bit value. Idx <<= 1;