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Be stricter in enforcing IT instruction predicate values, so that we don't end up trying to print out an illegal predicate.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138443 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
2011-08-24 17:21:43 +00:00
parent ddaa513fce
commit e234d02204
2 changed files with 15 additions and 0 deletions
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1
lib/Target/ARM/ARMInstrThumb2.td
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@@ -14,6 +14,7 @@
// IT block predicate field // IT block predicate field
def it_pred : Operand<i32> { def it_pred : Operand<i32> {
let PrintMethod = "printMandatoryPredicateOperand"; let PrintMethod = "printMandatoryPredicateOperand";
let DecoderMethod = "DecodeITCond";
} }
// IT block condition mask // IT block condition mask

14
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@@ -228,6 +228,8 @@ static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeITCond(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
#include "ARMGenDisassemblerTables.inc" #include "ARMGenDisassemblerTables.inc"
#include "ARMGenInstrInfo.inc" #include "ARMGenInstrInfo.inc"
@@ -3289,3 +3291,15 @@ static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
return S; return S;
} }
static DecodeStatus DecodeITCond(llvm::MCInst &Inst, unsigned Cond,
uint64_t Address, const void *Decoder) {
DecodeStatus S = Success;
if (Cond == 0xF) {
Cond = 0xE;
CHECK(S, Unpredictable);
}
Inst.addOperand(MCOperand::CreateImm(Cond));
return S;
}