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Thumb unconditional branch binary encoding. rdar://8754994
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121496 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1558,6 +1558,7 @@ unsigned ARMELFObjectWriter::GetRelocType(const MCValue &Target,
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case ARM::fixup_arm_thumb_bl:
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case ARM::fixup_arm_thumb_cb:
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case ARM::fixup_arm_thumb_cp:
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case ARM::fixup_arm_thumb_br:
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assert(0 && "Unimplemented"); break;
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case ARM::fixup_arm_branch:
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Type = ELF::R_ARM_CALL; break;
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@ -200,6 +200,9 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
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uint32_t Binary = (Value - 4) >> 1;
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return ((Binary & 0x20) << 9) | ((Binary & 0x1f) << 3);
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}
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case ARM::fixup_arm_thumb_br:
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// Offset by 4 and don't encode the lower bit, which is always 0.
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return ((Value - 4) >> 1) & 0x7ff;
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case ARM::fixup_arm_thumb_bcc:
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// Offset by 4 and don't encode the lower bit, which is always 0.
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return ((Value - 4) >> 1) & 0xff;
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@ -317,6 +320,7 @@ static unsigned getFixupKindNumBytes(unsigned Kind) {
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case ARM::fixup_arm_thumb_cp:
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return 1;
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case ARM::fixup_arm_thumb_br:
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case ARM::fixup_arm_thumb_cb:
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return 2;
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@ -175,6 +175,8 @@ namespace {
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const { return 0; }
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unsigned getThumbBLXTargetOpValue(const MachineInstr &MI, unsigned Op)
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const { return 0; }
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unsigned getThumbBRTargetOpValue(const MachineInstr &MI, unsigned Op)
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const { return 0; }
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unsigned getThumbBCCTargetOpValue(const MachineInstr &MI, unsigned Op)
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const { return 0; }
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unsigned getThumbCBTargetOpValue(const MachineInstr &MI, unsigned Op)
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@ -40,6 +40,9 @@ enum Fixups {
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// instructions.
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fixup_t2_branch,
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// fixup_arm_thumb_br - 12-bit fixup for Thumb B instructions.
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fixup_arm_thumb_br,
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// fixup_arm_thumb_blx - Fixup for Thumb BL instructions.
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fixup_arm_thumb_bl,
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@ -74,6 +74,10 @@ def t_imm_s4 : Operand<i32> {
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// Define Thumb specific addressing modes.
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def t_brtarget : Operand<OtherVT> {
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let EncoderMethod = "getThumbBRTargetOpValue";
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}
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def t_bcctarget : Operand<i32> {
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let EncoderMethod = "getThumbBCCTargetOpValue";
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}
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@ -492,11 +496,15 @@ let isCall = 1,
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let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
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let isPredicable = 1 in
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def tB : T1I<(outs), (ins brtarget:$target), IIC_Br,
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def tB : T1I<(outs), (ins t_brtarget:$target), IIC_Br,
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"b\t$target", [(br bb:$target)]>,
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T1Encoding<{1,1,1,0,0,?}>;
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T1Encoding<{1,1,1,0,0,?}> {
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bits<11> target;
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let Inst{10-0} = target;
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}
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// Far jump
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// FIXME: Encoding. This should probably be a pseudo for tBL
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let Defs = [LR] in
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def tBfar : TIx2<0b11110, 0b11, 1, (outs), (ins brtarget:$target), IIC_Br,
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"bl\t$target",[]>;
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@ -59,6 +59,7 @@ public:
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{ "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_thumb_cp", 1, 8, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_thumb_bcc", 1, 8, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_movt_hi16", 0, 16, 0 },
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{ "fixup_arm_movw_lo16", 0, 16, 0 },
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@ -101,6 +102,10 @@ public:
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uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
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uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
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uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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@ -457,6 +462,13 @@ getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
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return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx, Fixups);
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}
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/// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
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uint32_t ARMMCCodeEmitter::
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getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const {
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return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, Fixups);
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}
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/// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
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uint32_t ARMMCCodeEmitter::
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getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
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@ -587,6 +587,7 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
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IMM("neon_vcvt_imm32");
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MISC("brtarget", "kOperandTypeARMBranchTarget"); // ?
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MISC("t_brtarget", "kOperandTypeARMBranchTarget"); // ?
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MISC("t_bcctarget", "kOperandTypeARMBranchTarget"); // ?
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MISC("t_cbtarget", "kOperandTypeARMBranchTarget"); // ?
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MISC("bltarget", "kOperandTypeARMBranchTarget"); // ?
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