Rework braindead conditionals I put in yesterday.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111974 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2010-08-24 22:07:27 +00:00
parent 9f782d4dcf
commit e24d66f525

View File

@ -365,20 +365,18 @@ bool ARMFastISel::ARMLoadAlloca(const Instruction *I) {
Value *Op0 = I->getOperand(0); Value *Op0 = I->getOperand(0);
// Verify it's an alloca. // Verify it's an alloca.
const Instruction *Inst = dyn_cast<Instruction>(Op0); if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op0)) {
if (!Inst || Inst->getOpcode() != Instruction::Alloca) return false; DenseMap<const AllocaInst*, int>::iterator SI =
FuncInfo.StaticAllocaMap.find(AI);
const AllocaInst *AI = cast<AllocaInst>(Op0); if (SI != FuncInfo.StaticAllocaMap.end()) {
DenseMap<const AllocaInst*, int>::iterator SI = unsigned ResultReg = createResultReg(FixedRC);
FuncInfo.StaticAllocaMap.find(AI); TII.loadRegFromStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
ResultReg, SI->second, FixedRC,
if (SI != FuncInfo.StaticAllocaMap.end()) { TM.getRegisterInfo());
unsigned ResultReg = createResultReg(FixedRC); UpdateValueMap(I, ResultReg);
TII.loadRegFromStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt, return true;
ResultReg, SI->second, FixedRC, }
TM.getRegisterInfo());
UpdateValueMap(I, ResultReg);
return true;
} }
return false; return false;