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Rework braindead conditionals I put in yesterday.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111974 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -365,20 +365,18 @@ bool ARMFastISel::ARMLoadAlloca(const Instruction *I) {
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Value *Op0 = I->getOperand(0);
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Value *Op0 = I->getOperand(0);
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// Verify it's an alloca.
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// Verify it's an alloca.
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const Instruction *Inst = dyn_cast<Instruction>(Op0);
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if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op0)) {
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if (!Inst || Inst->getOpcode() != Instruction::Alloca) return false;
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DenseMap<const AllocaInst*, int>::iterator SI =
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FuncInfo.StaticAllocaMap.find(AI);
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const AllocaInst *AI = cast<AllocaInst>(Op0);
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if (SI != FuncInfo.StaticAllocaMap.end()) {
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DenseMap<const AllocaInst*, int>::iterator SI =
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unsigned ResultReg = createResultReg(FixedRC);
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FuncInfo.StaticAllocaMap.find(AI);
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TII.loadRegFromStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
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ResultReg, SI->second, FixedRC,
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if (SI != FuncInfo.StaticAllocaMap.end()) {
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TM.getRegisterInfo());
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unsigned ResultReg = createResultReg(FixedRC);
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UpdateValueMap(I, ResultReg);
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TII.loadRegFromStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
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return true;
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ResultReg, SI->second, FixedRC,
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}
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TM.getRegisterInfo());
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UpdateValueMap(I, ResultReg);
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return true;
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}
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}
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return false;
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return false;
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