6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-23 02:29:18 +00:00
Code Issues Projects Releases Wiki Activity

Add AVX SSE2 mask creation and conditional store instructions

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107306 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2010-06-30 18:38:10 +00:00
parent 61e4a0bc10
commit e26f14d150
3 changed files with 57 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
lib/Target/X86/X86InstrSSE.td
View File

@ -2839,29 +2839,55 @@ let Constraints = "$src1 = $dst" in
} // ExeDomain = SSEPackedInt
//===---------------------------------------------------------------------===//
// SSE2 - Packed Misc Integer Instructions
// SSE2 - Packed Mask Creation
//===---------------------------------------------------------------------===//
let ExeDomain = SSEPackedInt in {
// Mask creation
let isAsmParserOnly = 1 in
def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
"pmovmskb\t{$src, $dst|$dst, $src}",
[(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
"pmovmskb\t{$src, $dst|$dst, $src}",
[(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
// Conditional store
let Uses = [EDI] in
def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
"maskmovdqu\t{$mask, $src|$src, $mask}",
[(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
let Uses = [RDI] in
def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
"maskmovdqu\t{$mask, $src|$src, $mask}",
[(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
"pmovmskb\t{$src, $dst|$dst, $src}",
[(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
} // ExeDomain = SSEPackedInt
//===---------------------------------------------------------------------===//
// SSE2 - Conditional Store
//===---------------------------------------------------------------------===//
let ExeDomain = SSEPackedInt in {
let isAsmParserOnly = 1 in {
let Uses = [EDI] in
def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
(ins VR128:$src, VR128:$mask),
"maskmovdqu\t{$mask, $src|$src, $mask}",
[(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
let Uses = [RDI] in
def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
(ins VR128:$src, VR128:$mask),
"maskmovdqu\t{$mask, $src|$src, $mask}",
[(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
}
let Uses = [EDI] in
def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
"maskmovdqu\t{$mask, $src|$src, $mask}",
[(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
let Uses = [RDI] in
def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
"maskmovdqu\t{$mask, $src|$src, $mask}",
[(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
} // ExeDomain = SSEPackedInt
//===---------------------------------------------------------------------===//
// SSE2 - Packed Misc Integer Instructions
//===---------------------------------------------------------------------===//
// Flush cache
def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
"clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,

8
test/MC/AsmParser/X86/x86_32-encoding.s
View File

@ -11494,3 +11494,11 @@
// CHECK: encoding: [0xc5,0xf9,0xc5,0xc2,0x07]
vpextrw $7, %xmm2, %eax
// CHECK: vpmovmskb %xmm1, %eax
// CHECK: encoding: [0xc5,0xf9,0xd7,0xc1]
vpmovmskb %xmm1, %eax
// CHECK: vmaskmovdqu %xmm1, %xmm2
// CHECK: encoding: [0xc5,0xf9,0xf7,0xd1]
vmaskmovdqu %xmm1, %xmm2

8
test/MC/AsmParser/X86/x86_64-encoding.s
View File

@ -1534,3 +1534,11 @@ pshufb CPI1_0(%rip), %xmm1
// CHECK: encoding: [0xc4,0xc1,0x79,0xc5,0xc4,0x07]
vpextrw $7, %xmm12, %eax
// CHECK: vpmovmskb %xmm12, %eax
// CHECK: encoding: [0xc4,0xc1,0x79,0xd7,0xc4]
vpmovmskb %xmm12, %eax
// CHECK: vmaskmovdqu %xmm14, %xmm15
// CHECK: encoding: [0xc4,0x41,0x79,0xf7,0xfe]
vmaskmovdqu %xmm14, %xmm15