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R600/SI: Remove some unnecessary patterns from VINTRP multiclass

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DisableEncoding and Constraints can be set using let statements around
the multiclass defs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238148 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2015-05-25 16:15:56 +00:00
parent 38aad1c16a
commit e2b87dee1e
2 changed files with 9 additions and 11 deletions
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12
lib/Target/R600/SIInstrInfo.td
View File

@ -1771,16 +1771,12 @@ class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
SIMCInstr<opName, SISubtarget.VI>;
multiclass VINTRP_m <bits <2> op, dag outs, dag ins, string asm,
list<dag> pattern = [],
string disableEncoding = "", string constraints = ""> {
let DisableEncoding = disableEncoding,
Constraints = constraints in {
def "" : VINTRP_Pseudo <NAME, outs, ins, pattern>;
list<dag> pattern = []> {
def "" : VINTRP_Pseudo <NAME, outs, ins, pattern>;
def _si : VINTRP_Real_si <op, NAME, outs, ins, asm>;
def _si : VINTRP_Real_si <op, NAME, outs, ins, asm>;
def _vi : VINTRP_Real_vi <op, NAME, outs, ins, asm>;
}
def _vi : VINTRP_Real_vi <op, NAME, outs, ins, asm>;
}
//===----------------------------------------------------------------------===//

8
lib/Target/R600/SIInstructions.td
View File

@ -1461,15 +1461,17 @@ defm V_INTERP_P1_F32_16bank : V_INTERP_P1_F32_m;
} // End OtherPredicates = [has32BankLDS], Constraints = "@earlyclobber $dst"
let DisableEncoding = "$src0", Constraints = "$src0 = $dst" in {
defm V_INTERP_P2_F32 : VINTRP_m <
0x00000001,
(outs VGPR_32:$dst),
(ins VGPR_32:$src0, VGPR_32:$j, i32imm:$attr_chan, i32imm:$attr),
"v_interp_p2_f32 $dst, [$src0], $j, $attr_chan, $attr, [m0]",
[(set f32:$dst, (AMDGPUinterp_p2 f32:$src0, i32:$j, (i32 imm:$attr_chan),
(i32 imm:$attr)))],
"$src0",
"$src0 = $dst">;
(i32 imm:$attr)))]>;
} // End DisableEncoding = "$src0", Constraints = "$src0 = $dst"
defm V_INTERP_MOV_F32 : VINTRP_m <
0x00000002,