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R600/SI: Make private pointers be 32-bit.

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Different sized address spaces should theoretically work
most of the time now, and since 64-bit add is currently
disabled, using more 32-bit pointers fixes some cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197659 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2013-12-19 05:32:55 +00:00
parent 251b9217c7
commit e2c28ad84f
5 changed files with 43 additions and 16 deletions
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11
lib/Target/R600/AMDGPUTargetMachine.cpp
View File

@ -50,13 +50,12 @@ SchedCustomRegistry("r600", "Run R600's custom scheduler",
createR600MachineScheduler);
static std::string computeDataLayout(const AMDGPUSubtarget &ST) {
std::string Ret = "e";
std::string Ret = "e-p0:32:32";
if (!ST.is64bit())
Ret += "-p:32:32";
if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
Ret += "-p3:32:32";
if (ST.is64bit()) {
// 32-bit private, local, and region pointers. 64-bit global and constant.
Ret += "-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:64:64";
}
Ret += "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256"
"-v512:512-v1024:1024-v2048:2048-n32:64";

9
lib/Target/R600/SIISelLowering.cpp
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@ -137,7 +137,7 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand);
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
setOperationAction(ISD::FrameIndex, MVT::i64, Custom);
setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
setTargetDAGCombine(ISD::SELECT_CC);
@ -704,9 +704,7 @@ SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
if (Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS)
return SDValue();
SDValue TruncPtr = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
Load->getBasePtr(), DAG.getConstant(0, MVT::i32));
SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, TruncPtr,
SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
DAG.getConstant(2, MVT::i32));
SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
@ -793,8 +791,7 @@ SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
if (Store->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS)
return SDValue();
SDValue TruncPtr = DAG.getZExtOrTrunc(Store->getBasePtr(), DL, MVT::i32);
SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, TruncPtr,
SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Store->getBasePtr(),
DAG.getConstant(2, MVT::i32));
SDValue Chain = Store->getChain();
SmallVector<SDValue, 8> Values;

2
lib/Target/R600/SIInstrInfo.td
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@ -121,7 +121,7 @@ class SGPRImm <dag frag> : PatLeaf<frag, [{
return false;
}]>;
def FRAMEri64 : Operand<iPTR> {
def FRAMEri32 : Operand<iPTR> {
let MIOperandInfo = (ops SReg_32:$ptr, i32imm:$index);
}

6
lib/Target/R600/SIInstructions.td
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@ -1328,13 +1328,13 @@ def SI_KILL : InstSI <
let Uses = [EXEC], Defs = [EXEC,VCC,M0] in {
//defm SI_ : RegisterLoadStore <VReg_32, FRAMEri64, ADDRIndirect>;
//defm SI_ : RegisterLoadStore <VReg_32, FRAMEri, ADDRIndirect>;
let UseNamedOperandTable = 1 in {
def SI_RegisterLoad : AMDGPUShaderInst <
(outs VReg_32:$dst, SReg_64:$temp),
(ins FRAMEri64:$addr, i32imm:$chan),
(ins FRAMEri32:$addr, i32imm:$chan),
"", []
> {
let isRegisterLoad = 1;
@ -1343,7 +1343,7 @@ def SI_RegisterLoad : AMDGPUShaderInst <
class SIRegStore<dag outs> : AMDGPUShaderInst <
outs,
(ins VReg_32:$val, FRAMEri64:$addr, i32imm:$chan),
(ins VReg_32:$val, FRAMEri32:$addr, i32imm:$chan),
"", []
> {
let isRegisterStore = 1;

31
test/CodeGen/R600/array-ptr-calc-i32.ll Normal file
View File

@ -0,0 +1,31 @@
; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s
declare i32 @llvm.SI.tid() nounwind readnone
declare void @llvm.AMDGPU.barrier.local() nounwind noduplicate
; The required pointer calculations for the alloca'd actually requires
; an add and won't be folded into the addressing, which fails with a
; 64-bit pointer add. This should work since private pointers should
; be 32-bits.
; SI-LABEL: @test_private_array_ptr_calc:
; SI: V_ADD_I32_e32 [[PTRREG:v[0-9]+]]
; SI: V_MOVRELD_B32_e32 {{v[0-9]+}}, [[PTRREG]]
define void @test_private_array_ptr_calc(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %inA, i32 addrspace(1)* noalias %inB) {
%alloca = alloca [4 x i32], i32 4, align 16
%tid = call i32 @llvm.SI.tid() readnone
%a_ptr = getelementptr i32 addrspace(1)* %inA, i32 %tid
%b_ptr = getelementptr i32 addrspace(1)* %inB, i32 %tid
%a = load i32 addrspace(1)* %a_ptr
%b = load i32 addrspace(1)* %b_ptr
%result = add i32 %a, %b
%alloca_ptr = getelementptr [4 x i32]* %alloca, i32 1, i32 %b
store i32 %result, i32* %alloca_ptr, align 4
; Dummy call
call void @llvm.AMDGPU.barrier.local() nounwind noduplicate
%reload = load i32* %alloca_ptr, align 4
%out_ptr = getelementptr i32 addrspace(1)* %out, i32 %tid
store i32 %reload, i32 addrspace(1)* %out_ptr, align 4
ret void
}