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Rename MachineInstrInfo::getDescriptor to MachineInstrInfo::get

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4387 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2002-10-29 17:26:26 +00:00
parent 8f7802727f
commit e30eeaaf72
2 changed files with 72 additions and 68 deletions
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70
include/llvm/Target/MachineInstrInfo.h
View File

@@ -81,7 +81,6 @@ struct MachineInstrDescriptor {
class MachineInstrInfo { class MachineInstrInfo {
private:
const MachineInstrDescriptor* desc; // raw array to allow static init'n const MachineInstrDescriptor* desc; // raw array to allow static init'n
unsigned descSize; // number of entries in the desc array unsigned descSize; // number of entries in the desc array
unsigned numRealOpCodes; // number of non-dummy op codes unsigned numRealOpCodes; // number of non-dummy op codes
@@ -96,25 +95,28 @@ public:
unsigned getNumRealOpCodes() const { return numRealOpCodes; } unsigned getNumRealOpCodes() const { return numRealOpCodes; }
unsigned getNumTotalOpCodes() const { return descSize; } unsigned getNumTotalOpCodes() const { return descSize; }
const MachineInstrDescriptor& getDescriptor(MachineOpCode opCode) const { /// get - Return the machine instruction descriptor that corresponds to the
/// specified instruction opcode.
///
const MachineInstrDescriptor& get(MachineOpCode opCode) const {
assert(opCode >= 0 && opCode < (int)descSize); assert(opCode >= 0 && opCode < (int)descSize);
return desc[opCode]; return desc[opCode];
} }
int getNumOperands(MachineOpCode opCode) const { int getNumOperands(MachineOpCode opCode) const {
return getDescriptor(opCode).numOperands; return get(opCode).numOperands;
} }
int getResultPos(MachineOpCode opCode) const { int getResultPos(MachineOpCode opCode) const {
return getDescriptor(opCode).resultPos; return get(opCode).resultPos;
} }
unsigned getNumDelaySlots(MachineOpCode opCode) const { unsigned getNumDelaySlots(MachineOpCode opCode) const {
return getDescriptor(opCode).numDelaySlots; return get(opCode).numDelaySlots;
} }
InstrSchedClass getSchedClass(MachineOpCode opCode) const { InstrSchedClass getSchedClass(MachineOpCode opCode) const {
return getDescriptor(opCode).schedClass; return get(opCode).schedClass;
} }
// //
@@ -122,66 +124,66 @@ public:
// flags listed above. // flags listed above.
// //
unsigned getIClass(MachineOpCode opCode) const { unsigned getIClass(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass; return get(opCode).iclass;
} }
bool isNop(MachineOpCode opCode) const { bool isNop(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_NOP_FLAG; return get(opCode).iclass & M_NOP_FLAG;
} }
bool isBranch(MachineOpCode opCode) const { bool isBranch(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_BRANCH_FLAG; return get(opCode).iclass & M_BRANCH_FLAG;
} }
bool isCall(MachineOpCode opCode) const { bool isCall(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_CALL_FLAG; return get(opCode).iclass & M_CALL_FLAG;
} }
bool isReturn(MachineOpCode opCode) const { bool isReturn(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_RET_FLAG; return get(opCode).iclass & M_RET_FLAG;
} }
bool isControlFlow(MachineOpCode opCode) const { bool isControlFlow(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_BRANCH_FLAG return get(opCode).iclass & M_BRANCH_FLAG
|| getDescriptor(opCode).iclass & M_CALL_FLAG || get(opCode).iclass & M_CALL_FLAG
|| getDescriptor(opCode).iclass & M_RET_FLAG; || get(opCode).iclass & M_RET_FLAG;
} }
bool isArith(MachineOpCode opCode) const { bool isArith(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_ARITH_FLAG; return get(opCode).iclass & M_ARITH_FLAG;
} }
bool isCCInstr(MachineOpCode opCode) const { bool isCCInstr(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_CC_FLAG; return get(opCode).iclass & M_CC_FLAG;
} }
bool isLogical(MachineOpCode opCode) const { bool isLogical(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_LOGICAL_FLAG; return get(opCode).iclass & M_LOGICAL_FLAG;
} }
bool isIntInstr(MachineOpCode opCode) const { bool isIntInstr(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_INT_FLAG; return get(opCode).iclass & M_INT_FLAG;
} }
bool isFloatInstr(MachineOpCode opCode) const { bool isFloatInstr(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_FLOAT_FLAG; return get(opCode).iclass & M_FLOAT_FLAG;
} }
bool isConditional(MachineOpCode opCode) const { bool isConditional(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_CONDL_FLAG; return get(opCode).iclass & M_CONDL_FLAG;
} }
bool isLoad(MachineOpCode opCode) const { bool isLoad(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_LOAD_FLAG; return get(opCode).iclass & M_LOAD_FLAG;
} }
bool isPrefetch(MachineOpCode opCode) const { bool isPrefetch(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_PREFETCH_FLAG; return get(opCode).iclass & M_PREFETCH_FLAG;
} }
bool isLoadOrPrefetch(MachineOpCode opCode) const { bool isLoadOrPrefetch(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_LOAD_FLAG return get(opCode).iclass & M_LOAD_FLAG
|| getDescriptor(opCode).iclass & M_PREFETCH_FLAG; || get(opCode).iclass & M_PREFETCH_FLAG;
} }
bool isStore(MachineOpCode opCode) const { bool isStore(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_STORE_FLAG; return get(opCode).iclass & M_STORE_FLAG;
} }
bool isMemoryAccess(MachineOpCode opCode) const { bool isMemoryAccess(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_LOAD_FLAG return get(opCode).iclass & M_LOAD_FLAG
|| getDescriptor(opCode).iclass & M_PREFETCH_FLAG || get(opCode).iclass & M_PREFETCH_FLAG
|| getDescriptor(opCode).iclass & M_STORE_FLAG; || get(opCode).iclass & M_STORE_FLAG;
} }
bool isDummyPhiInstr(const MachineOpCode opCode) const { bool isDummyPhiInstr(const MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_DUMMY_PHI_FLAG; return get(opCode).iclass & M_DUMMY_PHI_FLAG;
} }
bool isPseudoInstr(const MachineOpCode opCode) const { bool isPseudoInstr(const MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_PSEUDO_FLAG; return get(opCode).iclass & M_PSEUDO_FLAG;
} }
// Check if an instruction can be issued before its operands are ready, // Check if an instruction can be issued before its operands are ready,
@@ -201,11 +203,11 @@ public:
// Latencies for individual instructions and instruction pairs // Latencies for individual instructions and instruction pairs
// //
virtual int minLatency(MachineOpCode opCode) const { virtual int minLatency(MachineOpCode opCode) const {
return getDescriptor(opCode).latency; return get(opCode).latency;
} }
virtual int maxLatency(MachineOpCode opCode) const { virtual int maxLatency(MachineOpCode opCode) const {
return getDescriptor(opCode).latency; return get(opCode).latency;
} }
// //
@@ -229,8 +231,8 @@ public:
// //
virtual uint64_t maxImmedConstant(MachineOpCode opCode, virtual uint64_t maxImmedConstant(MachineOpCode opCode,
bool &isSignExtended) const { bool &isSignExtended) const {
isSignExtended = getDescriptor(opCode).immedIsSignExtended; isSignExtended = get(opCode).immedIsSignExtended;
return getDescriptor(opCode).maxImmedConst; return get(opCode).maxImmedConst;
} }
//------------------------------------------------------------------------- //-------------------------------------------------------------------------

70
include/llvm/Target/TargetInstrInfo.h
View File

@@ -81,7 +81,6 @@ struct MachineInstrDescriptor {
class MachineInstrInfo { class MachineInstrInfo {
private:
const MachineInstrDescriptor* desc; // raw array to allow static init'n const MachineInstrDescriptor* desc; // raw array to allow static init'n
unsigned descSize; // number of entries in the desc array unsigned descSize; // number of entries in the desc array
unsigned numRealOpCodes; // number of non-dummy op codes unsigned numRealOpCodes; // number of non-dummy op codes
@@ -96,25 +95,28 @@ public:
unsigned getNumRealOpCodes() const { return numRealOpCodes; } unsigned getNumRealOpCodes() const { return numRealOpCodes; }
unsigned getNumTotalOpCodes() const { return descSize; } unsigned getNumTotalOpCodes() const { return descSize; }
const MachineInstrDescriptor& getDescriptor(MachineOpCode opCode) const { /// get - Return the machine instruction descriptor that corresponds to the
/// specified instruction opcode.
///
const MachineInstrDescriptor& get(MachineOpCode opCode) const {
assert(opCode >= 0 && opCode < (int)descSize); assert(opCode >= 0 && opCode < (int)descSize);
return desc[opCode]; return desc[opCode];
} }
int getNumOperands(MachineOpCode opCode) const { int getNumOperands(MachineOpCode opCode) const {
return getDescriptor(opCode).numOperands; return get(opCode).numOperands;
} }
int getResultPos(MachineOpCode opCode) const { int getResultPos(MachineOpCode opCode) const {
return getDescriptor(opCode).resultPos; return get(opCode).resultPos;
} }
unsigned getNumDelaySlots(MachineOpCode opCode) const { unsigned getNumDelaySlots(MachineOpCode opCode) const {
return getDescriptor(opCode).numDelaySlots; return get(opCode).numDelaySlots;
} }
InstrSchedClass getSchedClass(MachineOpCode opCode) const { InstrSchedClass getSchedClass(MachineOpCode opCode) const {
return getDescriptor(opCode).schedClass; return get(opCode).schedClass;
} }
// //
@@ -122,66 +124,66 @@ public:
// flags listed above. // flags listed above.
// //
unsigned getIClass(MachineOpCode opCode) const { unsigned getIClass(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass; return get(opCode).iclass;
} }
bool isNop(MachineOpCode opCode) const { bool isNop(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_NOP_FLAG; return get(opCode).iclass & M_NOP_FLAG;
} }
bool isBranch(MachineOpCode opCode) const { bool isBranch(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_BRANCH_FLAG; return get(opCode).iclass & M_BRANCH_FLAG;
} }
bool isCall(MachineOpCode opCode) const { bool isCall(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_CALL_FLAG; return get(opCode).iclass & M_CALL_FLAG;
} }
bool isReturn(MachineOpCode opCode) const { bool isReturn(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_RET_FLAG; return get(opCode).iclass & M_RET_FLAG;
} }
bool isControlFlow(MachineOpCode opCode) const { bool isControlFlow(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_BRANCH_FLAG return get(opCode).iclass & M_BRANCH_FLAG
|| getDescriptor(opCode).iclass & M_CALL_FLAG || get(opCode).iclass & M_CALL_FLAG
|| getDescriptor(opCode).iclass & M_RET_FLAG; || get(opCode).iclass & M_RET_FLAG;
} }
bool isArith(MachineOpCode opCode) const { bool isArith(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_ARITH_FLAG; return get(opCode).iclass & M_ARITH_FLAG;
} }
bool isCCInstr(MachineOpCode opCode) const { bool isCCInstr(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_CC_FLAG; return get(opCode).iclass & M_CC_FLAG;
} }
bool isLogical(MachineOpCode opCode) const { bool isLogical(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_LOGICAL_FLAG; return get(opCode).iclass & M_LOGICAL_FLAG;
} }
bool isIntInstr(MachineOpCode opCode) const { bool isIntInstr(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_INT_FLAG; return get(opCode).iclass & M_INT_FLAG;
} }
bool isFloatInstr(MachineOpCode opCode) const { bool isFloatInstr(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_FLOAT_FLAG; return get(opCode).iclass & M_FLOAT_FLAG;
} }
bool isConditional(MachineOpCode opCode) const { bool isConditional(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_CONDL_FLAG; return get(opCode).iclass & M_CONDL_FLAG;
} }
bool isLoad(MachineOpCode opCode) const { bool isLoad(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_LOAD_FLAG; return get(opCode).iclass & M_LOAD_FLAG;
} }
bool isPrefetch(MachineOpCode opCode) const { bool isPrefetch(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_PREFETCH_FLAG; return get(opCode).iclass & M_PREFETCH_FLAG;
} }
bool isLoadOrPrefetch(MachineOpCode opCode) const { bool isLoadOrPrefetch(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_LOAD_FLAG return get(opCode).iclass & M_LOAD_FLAG
|| getDescriptor(opCode).iclass & M_PREFETCH_FLAG; || get(opCode).iclass & M_PREFETCH_FLAG;
} }
bool isStore(MachineOpCode opCode) const { bool isStore(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_STORE_FLAG; return get(opCode).iclass & M_STORE_FLAG;
} }
bool isMemoryAccess(MachineOpCode opCode) const { bool isMemoryAccess(MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_LOAD_FLAG return get(opCode).iclass & M_LOAD_FLAG
|| getDescriptor(opCode).iclass & M_PREFETCH_FLAG || get(opCode).iclass & M_PREFETCH_FLAG
|| getDescriptor(opCode).iclass & M_STORE_FLAG; || get(opCode).iclass & M_STORE_FLAG;
} }
bool isDummyPhiInstr(const MachineOpCode opCode) const { bool isDummyPhiInstr(const MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_DUMMY_PHI_FLAG; return get(opCode).iclass & M_DUMMY_PHI_FLAG;
} }
bool isPseudoInstr(const MachineOpCode opCode) const { bool isPseudoInstr(const MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_PSEUDO_FLAG; return get(opCode).iclass & M_PSEUDO_FLAG;
} }
// Check if an instruction can be issued before its operands are ready, // Check if an instruction can be issued before its operands are ready,
@@ -201,11 +203,11 @@ public:
// Latencies for individual instructions and instruction pairs // Latencies for individual instructions and instruction pairs
// //
virtual int minLatency(MachineOpCode opCode) const { virtual int minLatency(MachineOpCode opCode) const {
return getDescriptor(opCode).latency; return get(opCode).latency;
} }
virtual int maxLatency(MachineOpCode opCode) const { virtual int maxLatency(MachineOpCode opCode) const {
return getDescriptor(opCode).latency; return get(opCode).latency;
} }
// //
@@ -229,8 +231,8 @@ public:
// //
virtual uint64_t maxImmedConstant(MachineOpCode opCode, virtual uint64_t maxImmedConstant(MachineOpCode opCode,
bool &isSignExtended) const { bool &isSignExtended) const {
isSignExtended = getDescriptor(opCode).immedIsSignExtended; isSignExtended = get(opCode).immedIsSignExtended;
return getDescriptor(opCode).maxImmedConst; return get(opCode).maxImmedConst;
} }
//------------------------------------------------------------------------- //-------------------------------------------------------------------------