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Handle sitofp between v4f64 <- v4i32. Fix PR10559

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137114 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2011-08-09 05:48:01 +00:00
parent f5b757642d
commit e321d7ffc5
2 changed files with 28 additions and 1 deletions
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22
lib/Target/X86/X86ISelLowering.cpp
View File

@ -969,6 +969,9 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
// sint_to_fp between different vector types needs custom handling
setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Custom);
setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
@ -7078,6 +7081,24 @@ SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const
SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
SelectionDAG &DAG) const {
EVT SrcVT = Op.getOperand(0).getValueType();
EVT DstVT = Op.getValueType();
DebugLoc dl = Op.getDebugLoc();
if (SrcVT.isVector() && DstVT.isVector()) {
unsigned SrcVTSize = SrcVT.getSizeInBits();
unsigned DstVTSize = DstVT.getSizeInBits();
// Support directly by the target
if (SrcVTSize == DstVTSize)
return Op;
// Handle v4f64 = sitofp v4i32
if (DstVT != MVT::v4f64 && SrcVT != MVT::v4i32)
return SDValue();
SDValue V = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Op.getOperand(0));
return DAG.getNode(ISD::FP_EXTEND, dl, DstVT, V);
}
if (SrcVT.isVector())
return SDValue();
@ -7094,7 +7115,6 @@ SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
return Op;
}
DebugLoc dl = Op.getDebugLoc();
unsigned Size = SrcVT.getSizeInBits()/8;
MachineFunction &MF = DAG.getMachineFunction();
int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);

7
test/CodeGen/X86/avx-cvt.ll
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@ -6,6 +6,13 @@ define <8 x float> @sitofp00(<8 x i32> %a) nounwind {
ret <8 x float> %b
}
; CHECK: vcvtdq2ps
; CHECK-NEXT: vcvtps2pd
define <4 x double> @sitofp01(<4 x i32> %a) {
%b = sitofp <4 x i32> %a to <4 x double>
ret <4 x double> %b
}
; CHECK: vcvttps2dq %ymm
define <8 x i32> @fptosi00(<8 x float> %a) nounwind {
%b = fptosi <8 x float> %a to <8 x i32>