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https://github.com/c64scene-ar/llvm-6502.git
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Replace TargetInstrInfo::isInvariantLoad and its target-specific
implementations with a new MachineInstr::isInvariantLoad, which uses MachineMemOperands and is target-independent. This brings MachineLICM and other functionality to targets which previously lacked an isInvariantLoad implementation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83475 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -26,6 +26,7 @@
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namespace llvm {
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class AliasAnalysis;
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class TargetInstrDesc;
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class TargetInstrInfo;
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class TargetRegisterInfo;
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@ -286,6 +287,13 @@ public:
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/// have no volatile memory references.
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bool hasVolatileMemoryRef() const;
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/// isInvariantLoad - Return true if this instruction is loading from a
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/// location whose value is invariant across the function. For example,
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/// loading a value from the constant pool or from from the argument area of
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/// a function if it does not change. This should only return true of *all*
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/// loads the instruction does are invariant (if it does multiple loads).
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bool isInvariantLoad(AliasAnalysis *AA = 0) const;
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//
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// Debugging support
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//
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@ -157,16 +157,6 @@ public:
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unsigned DestReg, unsigned SubIdx,
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const MachineInstr *Orig) const = 0;
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/// isInvariantLoad - Return true if the specified instruction (which is
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/// marked mayLoad) is loading from a location whose value is invariant across
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/// the function. For example, loading a value from the constant pool or from
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/// from the argument area of a function if it does not change. This should
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/// only return true of *all* loads the instruction does are invariant (if it
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/// does multiple loads).
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virtual bool isInvariantLoad(const MachineInstr *MI) const {
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return false;
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}
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/// convertToThreeAddress - This method must be implemented by targets that
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/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
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/// may be able to convert a two-address instruction into one or more true
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@ -24,6 +24,7 @@
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetInstrDesc.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/Analysis/DebugInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/LeakDetector.h"
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@ -946,7 +947,7 @@ bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
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// destination. The check for isInvariantLoad gives the targe the chance to
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// classify the load as always returning a constant, e.g. a constant pool
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// load.
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if (TID->mayLoad() && !TII->isInvariantLoad(this))
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if (TID->mayLoad() && !isInvariantLoad())
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// Otherwise, this is a real load. If there is a store between the load and
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// end of block, or if the load is volatile, we can't move it.
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return !SawStore && !hasVolatileMemoryRef();
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@ -1005,6 +1006,46 @@ bool MachineInstr::hasVolatileMemoryRef() const {
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return false;
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}
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/// isInvariantLoad - Return true if this instruction is loading from a
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/// location whose value is invariant across the function. For example,
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/// loading a value from the constant pool or from from the argument area
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/// of a function if it does not change. This should only return true of
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/// *all* loads the instruction does are invariant (if it does multiple loads).
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bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
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// If the instruction doesn't load at all, it isn't an invariant load.
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if (!TID->mayLoad())
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return false;
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// If the instruction has lost its memoperands, conservatively assume that
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// it may not be an invariant load.
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if (memoperands_empty())
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return false;
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const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
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for (mmo_iterator I = memoperands_begin(),
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E = memoperands_end(); I != E; ++I) {
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if ((*I)->isVolatile()) return false;
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if ((*I)->isStore()) return false;
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if (const Value *V = (*I)->getValue()) {
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// A load from a constant PseudoSourceValue is invariant.
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if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
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if (PSV->isConstant(MFI))
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continue;
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// If we have an AliasAnalysis, ask it whether the memory is constant.
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if (AA && AA->pointsToConstantMemory(V))
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continue;
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}
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// Otherwise assume conservatively.
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return false;
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}
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// Everything checks out.
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return true;
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}
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void MachineInstr::dump() const {
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errs() << " " << *this;
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}
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@ -28,6 +28,7 @@
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/Compiler.h"
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@ -47,6 +48,7 @@ namespace {
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BitVector AllocatableSet;
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// Various analyses that we use...
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AliasAnalysis *AA; // Alias analysis info.
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MachineLoopInfo *LI; // Current MachineLoopInfo
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MachineDominatorTree *DT; // Machine dominator tree for the cur loop
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MachineRegisterInfo *RegInfo; // Machine register information
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@ -72,6 +74,7 @@ namespace {
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AU.setPreservesCFG();
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AU.addRequired<MachineLoopInfo>();
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AU.addRequired<MachineDominatorTree>();
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AU.addRequired<AliasAnalysis>();
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AU.addPreserved<MachineLoopInfo>();
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AU.addPreserved<MachineDominatorTree>();
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MachineFunctionPass::getAnalysisUsage(AU);
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@ -144,6 +147,7 @@ bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
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// Get our Loop information...
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LI = &getAnalysis<MachineLoopInfo>();
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DT = &getAnalysis<MachineDominatorTree>();
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AA = &getAnalysis<AliasAnalysis>();
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for (MachineLoopInfo::iterator
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I = LI->begin(), E = LI->end(); I != E; ++I) {
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@ -214,7 +218,7 @@ bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
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// Okay, this instruction does a load. As a refinement, we allow the target
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// to decide whether the loaded value is actually a constant. If so, we can
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// actually use it as a load.
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if (!TII->isInvariantLoad(&I))
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if (!I.isInvariantLoad(AA))
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// FIXME: we should be able to sink loads with no other side effects if
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// there is nothing that can change memory from here until the end of
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// block. This is a trivial form of alias analysis.
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@ -259,8 +263,6 @@ bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
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// Don't hoist an instruction that uses or defines a physical register.
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if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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// If this is a physical register use, we can't move it. If it is a def,
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// we can move it, but only if the def is dead.
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if (MO.isUse()) {
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// If the physreg has no defs anywhere, it's just an ambient register
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// and we can freely move its uses. Alternatively, if it's allocatable,
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@ -178,8 +178,6 @@ bool MachineSinking::SinkInstruction(MachineInstr *MI, bool &SawStore) {
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if (Reg == 0) continue;
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if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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// If this is a physical register use, we can't move it. If it is a def,
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// we can move it, but only if the def is dead.
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if (MO.isUse()) {
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// If the physreg has no defs anywhere, it's just an ambient register
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// and we can freely move its uses. Alternatively, if it's allocatable,
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// Treat all other stores conservatively.
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goto new_chain;
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} else if (TID.mayLoad()) {
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if (TII->isInvariantLoad(MI)) {
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if (MI->isInvariantLoad()) {
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// Invariant load, no chain dependencies needed!
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} else if (const Value *V = getUnderlyingObjectForInstr(MI)) {
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// A load from a specific PseudoSourceValue. Add precise dependencies.
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@ -266,30 +266,6 @@ unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
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return 0;
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}
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bool SystemZInstrInfo::isInvariantLoad(const MachineInstr *MI) const {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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// Loads from constant pools are trivially invariant.
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if (MO.isCPI())
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return true;
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if (MO.isGlobal())
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return isGVStub(MO.getGlobal(), TM);
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// If this is a load from an invariant stack slot, the load is a constant.
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if (MO.isFI()) {
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const MachineFrameInfo &MFI =
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*MI->getParent()->getParent()->getFrameInfo();
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int Idx = MO.getIndex();
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return MFI.isFixedObjectIndex(Idx) && MFI.isImmutableObjectIndex(Idx);
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}
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}
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// All other instances of these instructions are presumed to have other
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// issues.
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return false;
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}
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bool
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SystemZInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
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unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
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unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;
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bool isInvariantLoad(const MachineInstr *MI) const;
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virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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NewMI->getOperand(0).setSubReg(SubIdx);
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}
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/// isInvariantLoad - Return true if the specified instruction (which is marked
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/// mayLoad) is loading from a location whose value is invariant across the
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/// function. For example, loading a value from the constant pool or from
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/// from the argument area of a function if it does not change. This should
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/// only return true of *all* loads the instruction does are invariant (if it
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/// does multiple loads).
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bool X86InstrInfo::isInvariantLoad(const MachineInstr *MI) const {
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// This code cares about loads from three cases: constant pool entries,
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// invariant argument slots, and global stubs. In order to handle these cases
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// for all of the myriad of X86 instructions, we just scan for a CP/FI/GV
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// operand and base our analysis on it. This is safe because the address of
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// none of these three cases is ever used as anything other than a load base
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// and X86 doesn't have any instructions that load from multiple places.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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// Loads from constant pools are trivially invariant.
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if (MO.isCPI())
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return true;
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if (MO.isGlobal())
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return isGlobalStubReference(MO.getTargetFlags());
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// If this is a load from an invariant stack slot, the load is a constant.
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if (MO.isFI()) {
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const MachineFrameInfo &MFI =
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*MI->getParent()->getParent()->getFrameInfo();
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int Idx = MO.getIndex();
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return MFI.isFixedObjectIndex(Idx) && MFI.isImmutableObjectIndex(Idx);
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}
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}
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// All other instances of these instructions are presumed to have other
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// issues.
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return false;
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}
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/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
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/// is not marked dead.
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static bool hasLiveCondCodeDef(MachineInstr *MI) {
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unsigned DestReg, unsigned SubIdx,
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const MachineInstr *Orig) const;
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bool isInvariantLoad(const MachineInstr *MI) const;
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/// convertToThreeAddress - This method must be implemented by targets that
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/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
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/// may be able to convert a two-address instruction into a true
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return 0;
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}
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/// isInvariantLoad - Return true if the specified instruction (which is marked
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/// mayLoad) is loading from a location whose value is invariant across the
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/// function. For example, loading a value from the constant pool or from
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/// from the argument area of a function if it does not change. This should
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/// only return true of *all* loads the instruction does are invariant (if it
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/// does multiple loads).
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bool
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XCoreInstrInfo::isInvariantLoad(const MachineInstr *MI) const {
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// Loads from constants pools and loads from invariant argument slots are
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// invariant
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int Opcode = MI->getOpcode();
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if (Opcode == XCore::LDWCP_ru6 || Opcode == XCore::LDWCP_lru6) {
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return MI->getOperand(1).isCPI();
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}
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int FrameIndex;
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if (isLoadFromStackSlot(MI, FrameIndex)) {
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const MachineFrameInfo &MFI =
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*MI->getParent()->getParent()->getFrameInfo();
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return MFI.isFixedObjectIndex(FrameIndex) &&
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MFI.isImmutableObjectIndex(FrameIndex);
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}
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return false;
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}
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//===----------------------------------------------------------------------===//
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// Branch Analysis
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//===----------------------------------------------------------------------===//
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virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const;
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virtual bool isInvariantLoad(const MachineInstr *MI) const;
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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