From e357246c6b2f71fda64764b85e32d2004f5dd603 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Sun, 18 Dec 2005 02:10:39 +0000 Subject: [PATCH] Add initial support for global variables, and fix a bug in addr mode selection where we didn't select the operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24811 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Sparc/SparcISelDAGToDAG.cpp | 18 +++++++++++++++--- lib/Target/Sparc/SparcInstrInfo.td | 6 ++++++ lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp | 18 +++++++++++++++--- lib/Target/SparcV8/SparcV8InstrInfo.td | 6 ++++++ 4 files changed, 42 insertions(+), 6 deletions(-) diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp index d93f407a757..73b6722c6cc 100644 --- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -34,6 +34,8 @@ namespace V8ISD { CMPFCC, // Compare two FP operands, set fcc. BRICC, // Branch to dest on icc condition BRFCC, // Branch to dest on fcc condition + + Hi, Lo, // Hi/Lo operations, typically on a global address. }; } @@ -71,6 +73,9 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM) addRegisterClass(MVT::f32, V8::FPRegsRegisterClass); addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass); + // Custom legalize GlobalAddress nodes into LO/HI parts. + setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); + // Sparc doesn't have sext_inreg, replace them with shl/sra setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); @@ -239,6 +244,13 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) { return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond); } } + case ISD::GlobalAddress: { + GlobalValue *GV = cast(Op)->getGlobal(); + SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); + SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA); + SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA); + return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); + } } } @@ -297,8 +309,8 @@ bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1, if (isa(Addr.getOperand(1)) && Predicate_simm13(Addr.getOperand(1).Val)) return false; // Let the reg+imm pattern catch this! - R1 = Addr.getOperand(0); - R2 = Addr.getOperand(1); + R1 = Select(Addr.getOperand(0)); + R2 = Select(Addr.getOperand(1)); return true; } @@ -312,7 +324,7 @@ bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base, if (Addr.getOpcode() == ISD::ADD) { if (ConstantSDNode *CN = dyn_cast(Addr.getOperand(1))) if (Predicate_simm13(CN)) { - Base = Addr.getOperand(0); + Base = Select(Addr.getOperand(0)); Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32); return true; } diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index 6dbdeb545c2..eaa6691fee3 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -84,6 +84,8 @@ def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc>; def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>; def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>; +def V8hi : SDNode<"V8ISD::Hi", SDTIntUnaryOp>; +def V8lo : SDNode<"V8ISD::Lo", SDTIntUnaryOp>; //===----------------------------------------------------------------------===// // Instructions @@ -657,3 +659,7 @@ def : Pat<(i32 simm13:$val), // Arbitrary immediates. def : Pat<(i32 imm:$val), (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; + +// Global addresses +def : Pat<(V8hi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; +def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>; diff --git a/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp b/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp index d93f407a757..73b6722c6cc 100644 --- a/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp +++ b/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp @@ -34,6 +34,8 @@ namespace V8ISD { CMPFCC, // Compare two FP operands, set fcc. BRICC, // Branch to dest on icc condition BRFCC, // Branch to dest on fcc condition + + Hi, Lo, // Hi/Lo operations, typically on a global address. }; } @@ -71,6 +73,9 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM) addRegisterClass(MVT::f32, V8::FPRegsRegisterClass); addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass); + // Custom legalize GlobalAddress nodes into LO/HI parts. + setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); + // Sparc doesn't have sext_inreg, replace them with shl/sra setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); @@ -239,6 +244,13 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) { return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond); } } + case ISD::GlobalAddress: { + GlobalValue *GV = cast(Op)->getGlobal(); + SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); + SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA); + SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA); + return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); + } } } @@ -297,8 +309,8 @@ bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1, if (isa(Addr.getOperand(1)) && Predicate_simm13(Addr.getOperand(1).Val)) return false; // Let the reg+imm pattern catch this! - R1 = Addr.getOperand(0); - R2 = Addr.getOperand(1); + R1 = Select(Addr.getOperand(0)); + R2 = Select(Addr.getOperand(1)); return true; } @@ -312,7 +324,7 @@ bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base, if (Addr.getOpcode() == ISD::ADD) { if (ConstantSDNode *CN = dyn_cast(Addr.getOperand(1))) if (Predicate_simm13(CN)) { - Base = Addr.getOperand(0); + Base = Select(Addr.getOperand(0)); Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32); return true; } diff --git a/lib/Target/SparcV8/SparcV8InstrInfo.td b/lib/Target/SparcV8/SparcV8InstrInfo.td index 6dbdeb545c2..eaa6691fee3 100644 --- a/lib/Target/SparcV8/SparcV8InstrInfo.td +++ b/lib/Target/SparcV8/SparcV8InstrInfo.td @@ -84,6 +84,8 @@ def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc>; def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>; def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>; +def V8hi : SDNode<"V8ISD::Hi", SDTIntUnaryOp>; +def V8lo : SDNode<"V8ISD::Lo", SDTIntUnaryOp>; //===----------------------------------------------------------------------===// // Instructions @@ -657,3 +659,7 @@ def : Pat<(i32 simm13:$val), // Arbitrary immediates. def : Pat<(i32 imm:$val), (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; + +// Global addresses +def : Pat<(V8hi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; +def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;