mirror of
https://github.com/c64scene-ar/llvm-6502.git
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I'm starting to commit KNL backend. I'll push patches one-by-one. This patch includes support for the extended register set XMM16-31, YMM16-31, ZMM0-31.
The full ISA you can see here: http://software.intel.com/en-us/intel-isa-extensions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187030 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky
parent
9b3b286247
commit
e3809eed34
@ -86,6 +86,16 @@ def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX",
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def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
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"Enable AVX2 instructions",
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[FeatureAVX]>;
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def FeatureAVX512 : SubtargetFeature<"avx-512", "X86SSELevel", "AVX512",
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"Enable AVX-512 instructions",
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[FeatureAVX2]>;
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def FeatureERI : SubtargetFeature<"avx-512-eri", "HasERI", "true",
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"Enable AVX-512 Exponential and Reciprocal Instructions">;
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def FeatureCDI : SubtargetFeature<"avx-512-cdi", "HasCDI", "true",
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"Enable AVX-512 Conflict Detection Instructions">;
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def FeaturePFI : SubtargetFeature<"avx-512-pfi", "HasPFI", "true",
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"Enable AVX-512 PreFetch Instructions">;
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def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
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"Enable packed carry-less multiplication instructions",
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[FeatureSSE2]>;
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@ -227,6 +237,15 @@ def : ProcessorModel<"core-avx2", HaswellModel,
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FeatureBMI, FeatureBMI2, FeatureFMA, FeatureRTM,
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FeatureHLE]>;
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// KNL
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// FIXME: define KNL model
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def : ProcessorModel<"knl", HaswellModel,
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[FeatureAVX512, FeatureERI, FeatureCDI, FeaturePFI,
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FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
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FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
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FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
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FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE]>;
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def : Proc<"k6", [FeatureMMX]>;
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def : Proc<"k6-2", [Feature3DNow]>;
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def : Proc<"k6-3", [Feature3DNow]>;
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@ -49,6 +49,12 @@ def RetCC_X86Common : CallingConv<[
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CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
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CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>,
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// 512-bit vectors are returned in ZMM0 and ZMM1, when they fit. ZMM2 and ZMM3
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// can only be used by ABI non-compliant code. This vector type is only
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// supported while using the AVX-512 target feature.
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CCIfType<[v16i32, v8i64, v16f32, v8f64],
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CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>,
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// MMX vector types are always returned in MM0. If the target doesn't have
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// MM0, it doesn't support these vector types.
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CCIfType<[x86mmx], CCAssignToReg<[MM0]>>,
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@ -99,6 +105,10 @@ def RetCC_Intel_OCL_BI : CallingConv<[
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CCIfType<[v8f32, v4f64, v8i32, v4i64],
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CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>,
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// 512-bit FP vectors
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CCIfType<[v16f32, v8f64, v16i32, v8i64],
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CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>,
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// i32, i64 in the standard way
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CCDelegateTo<RetCC_X86Common>
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]>;
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@ -213,10 +223,15 @@ def CC_X86_64_C : CallingConv<[
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// fixed arguments to vararg functions are supposed to be passed in
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// registers. Actually modeling that would be a lot of work, though.
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CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
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CCIfSubtarget<"hasAVX()",
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CCIfSubtarget<"hasFp256()",
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CCAssignToReg<[YMM0, YMM1, YMM2, YMM3,
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YMM4, YMM5, YMM6, YMM7]>>>>,
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// The first 8 512-bit vector arguments are passed in ZMM registers.
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CCIfNotVarArg<CCIfType<[v16i32, v8i64, v16f32, v8f64],
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CCIfSubtarget<"hasAVX512()",
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CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]>>>>,
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// Integer/FP values get stored in stack slots that are 8 bytes in size and
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// 8-byte aligned if there are no more registers to hold them.
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CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
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@ -230,7 +245,11 @@ def CC_X86_64_C : CallingConv<[
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// 256-bit vectors get 32-byte stack slots that are 32-byte aligned.
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CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
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CCAssignToStack<32, 32>>
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CCAssignToStack<32, 32>>,
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// 512-bit vectors get 64-byte stack slots that are 64-byte aligned.
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CCIfType<[v16i32, v8i64, v16f32, v8f64],
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CCAssignToStack<64, 64>>
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]>;
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// Calling convention used on Win64
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@ -251,6 +270,9 @@ def CC_X86_Win64_C : CallingConv<[
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// 256 bit vectors are passed by pointer
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CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
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// 512 bit vectors are passed by pointer
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CCIfType<[v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
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// The first 4 MMX vector arguments are passed in GPRs.
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CCIfType<[x86mmx], CCBitConvertToType<i64>>,
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@ -345,7 +367,7 @@ def CC_X86_32_Common : CallingConv<[
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// The first 4 AVX 256-bit vector arguments are passed in YMM registers.
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CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
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CCIfSubtarget<"hasAVX()",
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CCIfSubtarget<"hasFp256()",
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CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>>>,
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// Other SSE vectors get 16-byte stack slots that are 16-byte aligned.
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@ -469,6 +491,10 @@ def CC_Intel_OCL_BI : CallingConv<[
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CCIfType<[v8f32, v4f64, v8i32, v4i64],
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CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>,
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// The 512-bit vector arguments are passed in ZMM registers.
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CCIfType<[v16f32, v8f64, v16i32, v8i64],
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CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>,
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CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>,
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CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64_C>>,
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CCDelegateTo<CC_X86_32_C>
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@ -535,6 +561,10 @@ def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12,
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R13, R14, R15,
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(sequence "YMM%u", 6, 15))>;
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def CSR_Win64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI,
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R12, R13, R14, R15,
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(sequence "ZMM%u", 6, 21),
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K4, K5, K6, K7)>;
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//Standard C + XMM 8-15
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def CSR_64_Intel_OCL_BI : CalleeSavedRegs<(add CSR_64,
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(sequence "XMM%u", 8, 15))>;
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@ -542,3 +572,7 @@ def CSR_64_Intel_OCL_BI : CalleeSavedRegs<(add CSR_64,
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//Standard C + YMM 8-15
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def CSR_64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add CSR_64,
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(sequence "YMM%u", 8, 15))>;
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def CSR_64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add CSR_64,
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(sequence "ZMM%u", 16, 31),
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K4, K5, K6, K7)>;
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@ -18595,6 +18595,11 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
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case MVT::v8f32:
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case MVT::v4f64:
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return std::make_pair(0U, &X86::VR256RegClass);
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case MVT::v8f64:
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case MVT::v16f32:
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case MVT::v16i32:
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case MVT::v8i64:
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return std::make_pair(0U, &X86::VR512RegClass);
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}
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break;
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}
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@ -18705,7 +18710,13 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
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}
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} else if (Res.second == &X86::FR32RegClass ||
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Res.second == &X86::FR64RegClass ||
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Res.second == &X86::VR128RegClass) {
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Res.second == &X86::VR128RegClass ||
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Res.second == &X86::VR256RegClass ||
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Res.second == &X86::FR32XRegClass ||
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Res.second == &X86::FR64XRegClass ||
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Res.second == &X86::VR128XRegClass ||
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Res.second == &X86::VR256XRegClass ||
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Res.second == &X86::VR512RegClass) {
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// Handle references to XMM physical registers that got mapped into the
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// wrong class. This can happen with constraints like {xmm0} where the
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// target independent register mapper will just pick the first match it can
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@ -18719,6 +18730,8 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
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Res.second = &X86::VR128RegClass;
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else if (X86::VR256RegClass.hasType(VT))
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Res.second = &X86::VR256RegClass;
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else if (X86::VR512RegClass.hasType(VT))
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Res.second = &X86::VR512RegClass;
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}
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return Res;
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@ -241,6 +241,11 @@ X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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case CallingConv::Intel_OCL_BI: {
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bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
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bool HasAVX512 = TM.getSubtarget<X86Subtarget>().hasAVX512();
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if (HasAVX512 && IsWin64)
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return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
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if (HasAVX512 && Is64Bit)
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return CSR_64_Intel_OCL_BI_AVX512_SaveList;
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if (HasAVX && IsWin64)
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return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
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if (HasAVX && Is64Bit)
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@ -275,8 +280,13 @@ X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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const uint32_t*
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X86RegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
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bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
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bool HasAVX512 = TM.getSubtarget<X86Subtarget>().hasAVX512();
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if (CC == CallingConv::Intel_OCL_BI) {
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if (IsWin64 && HasAVX512)
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return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
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if (Is64Bit && HasAVX512)
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return CSR_64_Intel_OCL_BI_AVX512_RegMask;
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if (IsWin64 && HasAVX)
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return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
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if (Is64Bit && HasAVX)
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@ -380,6 +390,12 @@ BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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Reserved.set(*AI);
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}
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}
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if (!Is64Bit || !TM.getSubtarget<X86Subtarget>().hasAVX512()) {
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for (unsigned n = 16; n != 32; ++n) {
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for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
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Reserved.set(*AI);
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}
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}
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return Reserved;
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}
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@ -690,4 +706,16 @@ unsigned getX86SubSuperRegister(unsigned Reg, MVT::SimpleValueType VT,
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}
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}
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}
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unsigned get512BitSuperRegister(unsigned Reg) {
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if (Reg >= X86::XMM0 && Reg <= X86::XMM31)
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return X86::ZMM0 + (Reg - X86::XMM0);
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if (Reg >= X86::YMM0 && Reg <= X86::YMM31)
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return X86::ZMM0 + (Reg - X86::YMM0);
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if (Reg >= X86::ZMM0 && Reg <= X86::ZMM31)
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return Reg;
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llvm_unreachable("Unexpected SIMD register");
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return 0;
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}
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}
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@ -137,6 +137,9 @@ public:
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// e.g. getX86SubSuperRegister(X86::EAX, MVT::i16) return X86:AX
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unsigned getX86SubSuperRegister(unsigned, MVT::SimpleValueType, bool High=false);
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//get512BitRegister - X86 utility - returns 512-bit super register
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unsigned get512BitSuperRegister(unsigned Reg);
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} // End llvm namespace
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#endif
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@ -26,6 +26,7 @@ let Namespace = "X86" in {
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def sub_16bit : SubRegIndex<16>;
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def sub_32bit : SubRegIndex<32>;
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def sub_xmm : SubRegIndex<128>;
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def sub_ymm : SubRegIndex<256>;
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}
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//===----------------------------------------------------------------------===//
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@ -186,28 +187,53 @@ def XMM12: X86Reg<"xmm12", 12>, DwarfRegNum<[29, -2, -2]>;
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def XMM13: X86Reg<"xmm13", 13>, DwarfRegNum<[30, -2, -2]>;
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def XMM14: X86Reg<"xmm14", 14>, DwarfRegNum<[31, -2, -2]>;
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def XMM15: X86Reg<"xmm15", 15>, DwarfRegNum<[32, -2, -2]>;
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def XMM16: X86Reg<"xmm16", 16>, DwarfRegNum<[60, -2, -2]>;
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def XMM17: X86Reg<"xmm17", 17>, DwarfRegNum<[61, -2, -2]>;
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def XMM18: X86Reg<"xmm18", 18>, DwarfRegNum<[62, -2, -2]>;
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def XMM19: X86Reg<"xmm19", 19>, DwarfRegNum<[63, -2, -2]>;
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def XMM20: X86Reg<"xmm20", 20>, DwarfRegNum<[64, -2, -2]>;
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def XMM21: X86Reg<"xmm21", 21>, DwarfRegNum<[65, -2, -2]>;
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def XMM22: X86Reg<"xmm22", 22>, DwarfRegNum<[66, -2, -2]>;
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def XMM23: X86Reg<"xmm23", 23>, DwarfRegNum<[67, -2, -2]>;
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def XMM24: X86Reg<"xmm24", 24>, DwarfRegNum<[68, -2, -2]>;
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def XMM25: X86Reg<"xmm25", 25>, DwarfRegNum<[69, -2, -2]>;
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def XMM26: X86Reg<"xmm26", 26>, DwarfRegNum<[70, -2, -2]>;
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def XMM27: X86Reg<"xmm27", 27>, DwarfRegNum<[71, -2, -2]>;
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def XMM28: X86Reg<"xmm28", 28>, DwarfRegNum<[72, -2, -2]>;
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def XMM29: X86Reg<"xmm29", 29>, DwarfRegNum<[73, -2, -2]>;
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def XMM30: X86Reg<"xmm30", 30>, DwarfRegNum<[74, -2, -2]>;
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def XMM31: X86Reg<"xmm31", 31>, DwarfRegNum<[75, -2, -2]>;
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} // CostPerUse
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// YMM Registers, used by AVX instructions
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// YMM0-15 registers, used by AVX instructions and
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// YMM16-31 registers, used by AVX-512 instructions.
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let SubRegIndices = [sub_xmm] in {
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def YMM0: X86Reg<"ymm0", 0, [XMM0]>, DwarfRegAlias<XMM0>;
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def YMM1: X86Reg<"ymm1", 1, [XMM1]>, DwarfRegAlias<XMM1>;
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def YMM2: X86Reg<"ymm2", 2, [XMM2]>, DwarfRegAlias<XMM2>;
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def YMM3: X86Reg<"ymm3", 3, [XMM3]>, DwarfRegAlias<XMM3>;
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def YMM4: X86Reg<"ymm4", 4, [XMM4]>, DwarfRegAlias<XMM4>;
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def YMM5: X86Reg<"ymm5", 5, [XMM5]>, DwarfRegAlias<XMM5>;
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def YMM6: X86Reg<"ymm6", 6, [XMM6]>, DwarfRegAlias<XMM6>;
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def YMM7: X86Reg<"ymm7", 7, [XMM7]>, DwarfRegAlias<XMM7>;
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def YMM8: X86Reg<"ymm8", 8, [XMM8]>, DwarfRegAlias<XMM8>;
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def YMM9: X86Reg<"ymm9", 9, [XMM9]>, DwarfRegAlias<XMM9>;
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def YMM10: X86Reg<"ymm10", 10, [XMM10]>, DwarfRegAlias<XMM10>;
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def YMM11: X86Reg<"ymm11", 11, [XMM11]>, DwarfRegAlias<XMM11>;
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def YMM12: X86Reg<"ymm12", 12, [XMM12]>, DwarfRegAlias<XMM12>;
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def YMM13: X86Reg<"ymm13", 13, [XMM13]>, DwarfRegAlias<XMM13>;
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def YMM14: X86Reg<"ymm14", 14, [XMM14]>, DwarfRegAlias<XMM14>;
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def YMM15: X86Reg<"ymm15", 15, [XMM15]>, DwarfRegAlias<XMM15>;
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foreach Index = 0-31 in {
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def YMM#Index : X86Reg<"ymm"#Index, Index, [!cast<X86Reg>("XMM"#Index)]>,
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DwarfRegAlias<!cast<X86Reg>("XMM"#Index)>;
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}
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}
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// ZMM Registers, used by AVX-512 instructions.
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let SubRegIndices = [sub_ymm] in {
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foreach Index = 0-31 in {
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def ZMM#Index : X86Reg<"zmm"#Index, Index, [!cast<X86Reg>("YMM"#Index)]>,
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DwarfRegAlias<!cast<X86Reg>("XMM"#Index)>;
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}
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}
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// Mask Registers, used by AVX-512 instructions.
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def K0 : X86Reg<"k0", 0>, DwarfRegNum<[118, -2, -2]>;
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def K1 : X86Reg<"k1", 1>, DwarfRegNum<[119, -2, -2]>;
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def K2 : X86Reg<"k2", 2>, DwarfRegNum<[120, -2, -2]>;
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def K3 : X86Reg<"k3", 3>, DwarfRegNum<[121, -2, -2]>;
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def K4 : X86Reg<"k4", 4>, DwarfRegNum<[122, -2, -2]>;
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def K5 : X86Reg<"k5", 5>, DwarfRegNum<[123, -2, -2]>;
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def K6 : X86Reg<"k6", 6>, DwarfRegNum<[124, -2, -2]>;
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def K7 : X86Reg<"k7", 7>, DwarfRegNum<[125, -2, -2]>;
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class STRegister<string n, bits<16> Enc, list<Register> A> : X86Reg<n, Enc> {
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let Aliases = A;
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}
|
||||
@ -421,3 +447,25 @@ def FPCCR : RegisterClass<"X86", [i16], 16, (add FPSW)> {
|
||||
let CopyCost = -1; // Don't allow copying of status registers.
|
||||
let isAllocatable = 0;
|
||||
}
|
||||
|
||||
// AVX-512 vector/mask registers.
|
||||
def VR512 : RegisterClass<"X86", [v16f32, v8f64, v16i32, v8i64], 512,
|
||||
(sequence "ZMM%u", 0, 31)>;
|
||||
|
||||
// Scalar AVX-512 floating point registers.
|
||||
def FR32X : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 31)>;
|
||||
|
||||
def FR64X : RegisterClass<"X86", [f64], 64, (add FR32X)>;
|
||||
|
||||
// Extended VR128 and VR256 for AVX-512 instructions
|
||||
def VR128X : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
|
||||
128, (add FR32X)>;
|
||||
def VR256X : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
|
||||
256, (sequence "YMM%u", 0, 31)>;
|
||||
|
||||
def VK8 : RegisterClass<"X86", [v8i1], 8, (sequence "K%u", 0, 7)>;
|
||||
def VK16 : RegisterClass<"X86", [v16i1], 16, (add VK8)>;
|
||||
|
||||
def VK8WM : RegisterClass<"X86", [v8i1], 8, (sub VK8, K0)>;
|
||||
def VK16WM : RegisterClass<"X86", [v16i1], 16, (add VK8WM)>;
|
||||
|
||||
|
||||
@ -42,7 +42,7 @@ enum Style {
|
||||
class X86Subtarget : public X86GenSubtargetInfo {
|
||||
protected:
|
||||
enum X86SSEEnum {
|
||||
NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2
|
||||
NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512
|
||||
};
|
||||
|
||||
enum X863DNowEnum {
|
||||
@ -169,6 +169,15 @@ protected:
|
||||
/// address generation (AG) time.
|
||||
bool LEAUsesAG;
|
||||
|
||||
/// Processor has AVX-512 PreFetch Instructions
|
||||
bool HasPFI;
|
||||
|
||||
/// Processor has AVX-512 Exponential and Reciprocal Instructions
|
||||
bool HasERI;
|
||||
|
||||
/// Processor has AVX-512 Conflict Detection Instructions
|
||||
bool HasCDI;
|
||||
|
||||
/// stackAlignment - The minimum alignment known to hold of the stack frame on
|
||||
/// entry to the function and which must be maintained by every function.
|
||||
unsigned stackAlignment;
|
||||
@ -249,6 +258,7 @@ public:
|
||||
bool hasSSE42() const { return X86SSELevel >= SSE42; }
|
||||
bool hasAVX() const { return X86SSELevel >= AVX; }
|
||||
bool hasAVX2() const { return X86SSELevel >= AVX2; }
|
||||
bool hasAVX512() const { return X86SSELevel >= AVX512; }
|
||||
bool hasFp256() const { return hasAVX(); }
|
||||
bool hasInt256() const { return hasAVX2(); }
|
||||
bool hasSSE4A() const { return HasSSE4A; }
|
||||
@ -282,6 +292,9 @@ public:
|
||||
bool padShortFunctions() const { return PadShortFunctions; }
|
||||
bool callRegIndirect() const { return CallRegIndirect; }
|
||||
bool LEAusesAG() const { return LEAUsesAG; }
|
||||
bool hasCDI() const { return HasCDI; }
|
||||
bool hasPFI() const { return HasPFI; }
|
||||
bool hasERI() const { return HasERI; }
|
||||
|
||||
bool isAtom() const { return X86ProcFamily == IntelAtom; }
|
||||
|
||||
|
||||
@ -105,23 +105,28 @@ FunctionPass *llvm::createX86IssueVZeroUpperPass() {
|
||||
}
|
||||
|
||||
static bool isYmmReg(unsigned Reg) {
|
||||
if (Reg >= X86::YMM0 && Reg <= X86::YMM15)
|
||||
return true;
|
||||
return (Reg >= X86::YMM0 && Reg <= X86::YMM31);
|
||||
}
|
||||
|
||||
return false;
|
||||
static bool isZmmReg(unsigned Reg) {
|
||||
return (Reg >= X86::ZMM0 && Reg <= X86::ZMM31);
|
||||
}
|
||||
|
||||
static bool checkFnHasLiveInYmm(MachineRegisterInfo &MRI) {
|
||||
for (MachineRegisterInfo::livein_iterator I = MRI.livein_begin(),
|
||||
E = MRI.livein_end(); I != E; ++I)
|
||||
if (isYmmReg(I->first))
|
||||
if (isYmmReg(I->first) || isZmmReg(I->first))
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool clobbersAllYmmRegs(const MachineOperand &MO) {
|
||||
for (unsigned reg = X86::YMM0; reg < X86::YMM15; ++reg) {
|
||||
for (unsigned reg = X86::YMM0; reg < X86::YMM31; ++reg) {
|
||||
if (!MO.clobbersPhysReg(reg))
|
||||
return false;
|
||||
}
|
||||
for (unsigned reg = X86::ZMM0; reg < X86::ZMM31; ++reg) {
|
||||
if (!MO.clobbersPhysReg(reg))
|
||||
return false;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user