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[Sparc] Use HWEncoding instead of unused Num field in Sparc register definitions. Also, correct the definitions of RETL and RET instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188738 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Venkatraman Govindaraju 2013-08-20 01:26:14 +00:00
parent ec28c7d8ec
commit e3b29fbc5f
2 changed files with 9 additions and 12 deletions
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4
lib/Target/Sparc/SparcInstrInfo.td
View File

@ -286,11 +286,11 @@ let usesCustomInserter = 1, Uses = [FCC] in {
// Section A.3 - Synthetic Instructions, p. 85 // Section A.3 - Synthetic Instructions, p. 85
// special cases of JMPL: // special cases of JMPL:
let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in { let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in {
let rd = O7.Num, rs1 = G0.Num in let rd = 0, rs1 = 15 in
def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val), def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
"jmp %o7+$val", [(retflag simm13:$val)]>; "jmp %o7+$val", [(retflag simm13:$val)]>;
let rd = I7.Num, rs1 = G0.Num in let rd = 0, rs1 = 31 in
def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val), def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
"jmp %i7+$val", []>; "jmp %i7+$val", []>;
} }

17
lib/Target/Sparc/SparcRegisterInfo.td
View File

@ -11,8 +11,8 @@
// Declarations that describe the Sparc register file // Declarations that describe the Sparc register file
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class SparcReg<string n> : Register<n> { class SparcReg<bits<16> Enc, string n> : Register<n> {
field bits<5> Num; let HWEncoding = Enc;
let Namespace = "SP"; let Namespace = "SP";
} }
@ -27,16 +27,13 @@ def sub_odd : SubRegIndex<32, 32>;
// Registers are identified with 5-bit ID numbers. // Registers are identified with 5-bit ID numbers.
// Ri - 32-bit integer registers // Ri - 32-bit integer registers
class Ri<bits<5> num, string n> : SparcReg<n> { class Ri<bits<16> Enc, string n> : SparcReg<Enc, n>;
let Num = num;
}
// Rf - 32-bit floating-point registers // Rf - 32-bit floating-point registers
class Rf<bits<5> num, string n> : SparcReg<n> { class Rf<bits<16> Enc, string n> : SparcReg<Enc, n>;
let Num = num;
}
// Rd - Slots in the FP register file for 64-bit floating-point values. // Rd - Slots in the FP register file for 64-bit floating-point values.
class Rd<bits<5> num, string n, list<Register> subregs> : SparcReg<n> { class Rd<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
let Num = num;
let SubRegs = subregs; let SubRegs = subregs;
let SubRegIndices = [sub_even, sub_odd]; let SubRegIndices = [sub_even, sub_odd];
let CoveredBySubRegs = 1; let CoveredBySubRegs = 1;