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https://github.com/c64scene-ar/llvm-6502.git
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[AVX512] Use X86VectorVTInfo in the masking helper classes and the FMAs
No functionality change. Makes the code more compact (see the FMA part). This needs a new type attribute MemOpFrag in X86VectorVTInfo. For now I only defined this in the simple cases. See the commment before the attribute. Diff of X86.td.expanded before and after is empty except for the appearance of the new attribute. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218637 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Adam Nemet
parent
4edcbaec90
commit
e3d2fcce41
@ -52,6 +52,14 @@ class X86VectorVTInfo<int NumElts, ValueType EltVT, RegisterClass rc,
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VTName)), VTName));
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PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
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// Load patterns used for memory operands. We only have this defined in
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// case of i64 element types for sub-512 integer vectors. For now, keep
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// MemOpFrag undefined in these cases.
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PatFrag MemOpFrag =
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!if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName),
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!if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName),
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!if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)));
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// The corresponding float type, e.g. v16f32 for v16i32
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// Note: For EltSize < 32, FloatVT is illegal and TableGen
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// fails to compile, so we choose FloatVT = VT
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@ -77,6 +85,8 @@ def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
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def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
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def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
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def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
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def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
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def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
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// "x" in v32i8x_info means RC = VR256X
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def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
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@ -107,24 +117,24 @@ def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
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// Common base class of AVX512_masking and AVX512_masking_3src.
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multiclass AVX512_masking_common<bits<8> O, Format F, dag Outs, dag Ins,
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dag MaskingIns, dag ZeroMaskingIns,
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multiclass AVX512_masking_common<bits<8> O, Format F, X86VectorVTInfo _,
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dag Outs,
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dag Ins, dag MaskingIns, dag ZeroMaskingIns,
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string OpcodeStr,
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string AttSrcAsm, string IntelSrcAsm,
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dag RHS, dag MaskingRHS, ValueType OpVT,
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RegisterClass RC, RegisterClass KRC,
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dag RHS, dag MaskingRHS,
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string MaskingConstraint = ""> {
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def NAME: AVX512<O, F, Outs, Ins,
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OpcodeStr#" \t{"#AttSrcAsm#", $dst|"#
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"$dst, "#IntelSrcAsm#"}",
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[(set RC:$dst, RHS)]>;
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[(set _.RC:$dst, RHS)]>;
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// Prefer over VMOV*rrk Pat<>
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let AddedComplexity = 20 in
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def NAME#k: AVX512<O, F, Outs, MaskingIns,
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OpcodeStr#" \t{"#AttSrcAsm#", $dst {${mask}}|"#
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"$dst {${mask}}, "#IntelSrcAsm#"}",
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[(set RC:$dst, MaskingRHS)]>,
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[(set _.RC:$dst, MaskingRHS)]>,
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EVEX_K {
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// In case of the 3src subclass this is overridden with a let.
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string Constraints = MaskingConstraint;
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@ -133,9 +143,9 @@ multiclass AVX512_masking_common<bits<8> O, Format F, dag Outs, dag Ins,
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def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
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OpcodeStr#" \t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
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"$dst {${mask}} {z}, "#IntelSrcAsm#"}",
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[(set RC:$dst,
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(vselect KRC:$mask, RHS,
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(OpVT (bitconvert
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[(set _.RC:$dst,
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(vselect _.KRCWM:$mask, RHS,
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(_.VT (bitconvert
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(v16i32 immAllZerosV)))))]>,
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EVEX_KZ;
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}
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@ -143,34 +153,31 @@ multiclass AVX512_masking_common<bits<8> O, Format F, dag Outs, dag Ins,
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// This multiclass generates the unconditional/non-masking, the masking and
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// the zero-masking variant of the instruction. In the masking case, the
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// perserved vector elements come from a new dummy input operand tied to $dst.
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multiclass AVX512_masking<bits<8> O, Format F, dag Outs, dag Ins,
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string OpcodeStr,
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multiclass AVX512_masking<bits<8> O, Format F, X86VectorVTInfo _,
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dag Outs, dag Ins, string OpcodeStr,
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string AttSrcAsm, string IntelSrcAsm,
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dag RHS, ValueType OpVT, RegisterClass RC,
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RegisterClass KRC> :
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AVX512_masking_common<O, F, Outs,
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Ins,
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!con((ins RC:$src0, KRC:$mask), Ins),
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!con((ins KRC:$mask), Ins),
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dag RHS> :
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AVX512_masking_common<O, F, _, Outs, Ins,
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!con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
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!con((ins _.KRCWM:$mask), Ins),
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OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
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(vselect KRC:$mask, RHS, RC:$src0), OpVT, RC, KRC,
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(vselect _.KRCWM:$mask, RHS, _.RC:$src0),
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"$src0 = $dst">;
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// Similar to AVX512_masking but in this case one of the source operands
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// ($src1) is already tied to $dst so we just use that for the preserved
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// vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
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// $src1.
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multiclass AVX512_masking_3src<bits<8> O, Format F, dag Outs, dag NonTiedIns,
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string OpcodeStr,
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multiclass AVX512_masking_3src<bits<8> O, Format F, X86VectorVTInfo _,
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dag Outs, dag NonTiedIns, string OpcodeStr,
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string AttSrcAsm, string IntelSrcAsm,
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dag RHS, ValueType OpVT,
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RegisterClass RC, RegisterClass KRC> :
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AVX512_masking_common<O, F, Outs,
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!con((ins RC:$src1), NonTiedIns),
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!con((ins RC:$src1, KRC:$mask), NonTiedIns),
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!con((ins RC:$src1, KRC:$mask), NonTiedIns),
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dag RHS> :
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AVX512_masking_common<O, F, _, Outs,
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!con((ins _.RC:$src1), NonTiedIns),
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!con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
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!con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
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OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
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(vselect KRC:$mask, RHS, RC:$src1), OpVT, RC, KRC>;
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(vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
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// Bitcasts between 512-bit vector types. Return the original type since
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// no instruction is needed for the conversion
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@ -3267,156 +3274,130 @@ let Predicates = [HasAVX512] in {
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// FMA - Fused Multiply Operations
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//
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let Constraints = "$src1 = $dst" in {
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multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
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RegisterClass RC, X86MemOperand x86memop,
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PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
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string BrdcstStr, SDNode OpNode, ValueType OpVT,
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RegisterClass KRC> {
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defm r: AVX512_masking_3src<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src2, RC:$src3),
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multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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X86VectorVTInfo _> {
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defm r: AVX512_masking_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src2, _.RC:$src3),
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OpcodeStr, "$src3, $src2", "$src2, $src3",
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(OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)), OpVT, RC, KRC>,
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(_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
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AVX512FMA3Base;
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let mayLoad = 1 in
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def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, x86memop:$src3),
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def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
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(ins _.RC:$src1, _.RC:$src2, _.MemOp:$src3),
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!strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
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(mem_frag addr:$src3))))]>;
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def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
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!strconcat(OpcodeStr, " \t{${src3}", BrdcstStr,
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", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
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[(set RC:$dst, (OpNode RC:$src1, RC:$src2,
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(OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
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[(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2,
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(_.MemOpFrag addr:$src3))))]>;
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def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
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(ins _.RC:$src1, _.RC:$src2, _.ScalarMemOp:$src3),
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!strconcat(OpcodeStr, " \t{${src3}", _.BroadcastStr,
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", $src2, $dst|$dst, $src2, ${src3}", _.BroadcastStr, "}"),
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[(set _.RC:$dst, (OpNode _.RC:$src1, _.RC:$src2,
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(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))]>, EVEX_B;
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}
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} // Constraints = "$src1 = $dst"
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let ExeDomain = SSEPackedSingle in {
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defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}",
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X86Fmadd, v16f32, VK16WM>, EVEX_V512,
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EVEX_CD8<32, CD8VF>;
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defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}",
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X86Fmsub, v16f32, VK16WM>, EVEX_V512,
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EVEX_CD8<32, CD8VF>;
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defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}",
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X86Fmaddsub, v16f32, VK16WM>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}",
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X86Fmsubadd, v16f32, VK16WM>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}",
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X86Fnmadd, v16f32, VK16WM>, EVEX_V512,
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EVEX_CD8<32, CD8VF>;
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defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}",
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X86Fnmsub, v16f32, VK16WM>, EVEX_V512,
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EVEX_CD8<32, CD8VF>;
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defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", X86Fmadd,
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v16f32_info>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", X86Fmsub,
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v16f32_info>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", X86Fmaddsub,
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v16f32_info>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", X86Fmsubadd,
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v16f32_info>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", X86Fnmadd,
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v16f32_info>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", X86Fnmsub,
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v16f32_info>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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}
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let ExeDomain = SSEPackedDouble in {
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defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}",
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X86Fmadd, v8f64, VK8WM>, EVEX_V512,
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VEX_W, EVEX_CD8<64, CD8VF>;
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defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}",
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X86Fmsub, v8f64, VK8WM>, EVEX_V512, VEX_W,
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EVEX_CD8<64, CD8VF>;
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defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}",
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X86Fmaddsub, v8f64, VK8WM>,
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defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", X86Fmadd,
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v8f64_info>,
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EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}",
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X86Fmsubadd, v8f64, VK8WM>,
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defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", X86Fmsub,
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v8f64_info>,
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EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", X86Fmaddsub,
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v8f64_info>,
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EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", X86Fmsubadd,
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v8f64_info>,
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EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", X86Fnmadd,
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v8f64_info>,
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EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", X86Fnmsub,
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v8f64_info>,
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EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}",
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X86Fnmadd, v8f64, VK8WM>, EVEX_V512, VEX_W,
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EVEX_CD8<64, CD8VF>;
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defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}",
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X86Fnmsub, v8f64, VK8WM>, EVEX_V512, VEX_W,
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EVEX_CD8<64, CD8VF>;
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}
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let Constraints = "$src1 = $dst" in {
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multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
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RegisterClass RC, X86MemOperand x86memop,
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PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
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string BrdcstStr, SDNode OpNode, ValueType OpVT> {
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multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
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X86VectorVTInfo _> {
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let mayLoad = 1 in
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def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, RC:$src3, x86memop:$src2),
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def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
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(ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
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!strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
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[(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
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def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
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!strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
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", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
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[(set RC:$dst, (OpNode RC:$src1,
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(OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
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[(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2),
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_.RC:$src3)))]>;
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def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
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(ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
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!strconcat(OpcodeStr, " \t{${src2}", _.BroadcastStr,
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", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
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[(set _.RC:$dst,
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(OpNode _.RC:$src1, (_.VT (X86VBroadcast
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(_.ScalarLdFrag addr:$src2))),
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_.RC:$src3))]>, EVEX_B;
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}
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} // Constraints = "$src1 = $dst"
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let ExeDomain = SSEPackedSingle in {
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defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}",
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X86Fmadd, v16f32>, EVEX_V512,
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EVEX_CD8<32, CD8VF>;
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defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}",
|
||||
X86Fmsub, v16f32>, EVEX_V512,
|
||||
EVEX_CD8<32, CD8VF>;
|
||||
defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
|
||||
memopv16f32, f32mem, loadf32, "{1to16}",
|
||||
X86Fmaddsub, v16f32>,
|
||||
EVEX_V512, EVEX_CD8<32, CD8VF>;
|
||||
defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
|
||||
memopv16f32, f32mem, loadf32, "{1to16}",
|
||||
X86Fmsubadd, v16f32>,
|
||||
EVEX_V512, EVEX_CD8<32, CD8VF>;
|
||||
defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
|
||||
memopv16f32, f32mem, loadf32, "{1to16}",
|
||||
X86Fnmadd, v16f32>, EVEX_V512,
|
||||
EVEX_CD8<32, CD8VF>;
|
||||
defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
|
||||
memopv16f32, f32mem, loadf32, "{1to16}",
|
||||
X86Fnmsub, v16f32>, EVEX_V512,
|
||||
EVEX_CD8<32, CD8VF>;
|
||||
defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", X86Fmadd,
|
||||
v16f32_info>,
|
||||
EVEX_V512, EVEX_CD8<32, CD8VF>;
|
||||
defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", X86Fmsub,
|
||||
v16f32_info>,
|
||||
EVEX_V512, EVEX_CD8<32, CD8VF>;
|
||||
defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", X86Fmaddsub,
|
||||
v16f32_info>,
|
||||
EVEX_V512, EVEX_CD8<32, CD8VF>;
|
||||
defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", X86Fmsubadd,
|
||||
v16f32_info>,
|
||||
EVEX_V512, EVEX_CD8<32, CD8VF>;
|
||||
defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", X86Fnmadd,
|
||||
v16f32_info>,
|
||||
EVEX_V512, EVEX_CD8<32, CD8VF>;
|
||||
defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", X86Fnmsub,
|
||||
v16f32_info>,
|
||||
EVEX_V512, EVEX_CD8<32, CD8VF>;
|
||||
}
|
||||
let ExeDomain = SSEPackedDouble in {
|
||||
defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
|
||||
memopv8f64, f64mem, loadf64, "{1to8}",
|
||||
X86Fmadd, v8f64>, EVEX_V512,
|
||||
VEX_W, EVEX_CD8<64, CD8VF>;
|
||||
defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
|
||||
memopv8f64, f64mem, loadf64, "{1to8}",
|
||||
X86Fmsub, v8f64>, EVEX_V512, VEX_W,
|
||||
EVEX_CD8<64, CD8VF>;
|
||||
defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
|
||||
memopv8f64, f64mem, loadf64, "{1to8}",
|
||||
X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
|
||||
EVEX_CD8<64, CD8VF>;
|
||||
defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
|
||||
memopv8f64, f64mem, loadf64, "{1to8}",
|
||||
X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
|
||||
EVEX_CD8<64, CD8VF>;
|
||||
defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
|
||||
memopv8f64, f64mem, loadf64, "{1to8}",
|
||||
X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
|
||||
EVEX_CD8<64, CD8VF>;
|
||||
defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
|
||||
memopv8f64, f64mem, loadf64, "{1to8}",
|
||||
X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
|
||||
EVEX_CD8<64, CD8VF>;
|
||||
defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", X86Fmadd,
|
||||
v8f64_info>,
|
||||
EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
|
||||
defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", X86Fmsub,
|
||||
v8f64_info>,
|
||||
EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
|
||||
defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", X86Fmaddsub,
|
||||
v8f64_info>,
|
||||
EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
|
||||
defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", X86Fmsubadd,
|
||||
v8f64_info>,
|
||||
EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
|
||||
defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", X86Fnmadd,
|
||||
v8f64_info>,
|
||||
EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
|
||||
defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", X86Fnmsub,
|
||||
v8f64_info>,
|
||||
EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
|
||||
}
|
||||
|
||||
// Scalar FMA
|
||||
@ -4841,13 +4822,12 @@ def : Pat<(v8i64 (X86Shufp VR512:$src1,
|
||||
(VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
|
||||
|
||||
multiclass avx512_valign<X86VectorVTInfo _> {
|
||||
defm rri : AVX512_masking<0x03, MRMSrcReg, (outs _.RC:$dst),
|
||||
defm rri : AVX512_masking<0x03, MRMSrcReg, _, (outs _.RC:$dst),
|
||||
(ins _.RC:$src1, _.RC:$src2, i8imm:$src3),
|
||||
"valign"##_.Suffix,
|
||||
"$src3, $src2, $src1", "$src1, $src2, $src3",
|
||||
(_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
|
||||
(i8 imm:$src3))),
|
||||
_.VT, _.RC, _.KRCWM>,
|
||||
(i8 imm:$src3)))>,
|
||||
AVX512AIi8Base, EVEX_4V;
|
||||
|
||||
// Also match valign of packed floats.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user