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Great renaming: Sparc --> SparcV9

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11826 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Brian Gaeke 2004-02-25 18:44:15 +00:00
parent adc1efe81c
commit e3d6807ab5
34 changed files with 375 additions and 375 deletions
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14
lib/Target/SparcV9/EmitBytecodeToAssembly.cpp
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@ -1,4 +1,4 @@
//===-- EmitBytecodeToAssembly.cpp - Emit bytecode to Sparc .s File --------==//
//===-- EmitBytecodeToAssembly.cpp - Emit bytecode to SparcV9 .s File --------==//
//
// The LLVM Compiler Infrastructure
//
@ -13,7 +13,7 @@
//
//===----------------------------------------------------------------------===//
#include "SparcInternals.h"
#include "SparcV9Internals.h"
#include "llvm/Pass.h"
#include "llvm/Bytecode/Writer.h"
#include <iostream>
@ -86,13 +86,13 @@ namespace {
<< "\n";
}
// SparcBytecodeWriter - Write bytecode out to a stream that is sparc'ified
class SparcBytecodeWriter : public Pass {
// SparcV9BytecodeWriter - Write bytecode out to a stream that is sparc'ified
class SparcV9BytecodeWriter : public Pass {
std::ostream &Out;
public:
SparcBytecodeWriter(std::ostream &out) : Out(out) {}
SparcV9BytecodeWriter(std::ostream &out) : Out(out) {}
const char *getPassName() const { return "Emit Bytecode to Sparc Assembly";}
const char *getPassName() const { return "Emit Bytecode to SparcV9 Assembly";}
virtual bool run(Module &M) {
// Write an object containing the bytecode to the SPARC assembly stream
@ -113,7 +113,7 @@ namespace {
} // end anonymous namespace
Pass *createBytecodeAsmPrinterPass(std::ostream &Out) {
return new SparcBytecodeWriter(Out);
return new SparcV9BytecodeWriter(Out);
}
} // End llvm namespace

2
lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp
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@ -23,7 +23,7 @@
#include "llvm/Constants.h"
#include "llvm/BasicBlock.h"
#include "llvm/DerivedTypes.h"
#include "../SparcInstrSelectionSupport.h"
#include "../SparcV9InstrSelectionSupport.h"
namespace llvm {

2
lib/Target/SparcV9/InstrSelection/Makefile
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@ -9,6 +9,6 @@
LEVEL = ../../../..
DIRS =
LIBRARYNAME = select
LIBRARYNAME = sparcv9select
include $(LEVEL)/Makefile.common

2
lib/Target/SparcV9/LiveVar/BBLiveVar.cpp
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@ -17,7 +17,7 @@
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/Support/CFG.h"
#include "Support/SetOperations.h"
#include "../SparcInternals.h"
#include "../SparcV9Internals.h"
namespace llvm {

2
lib/Target/SparcV9/LiveVar/Makefile
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@ -8,7 +8,7 @@
##===----------------------------------------------------------------------===##
LEVEL = ../../../..
LIBRARYNAME = livevar
LIBRARYNAME = sparcv9livevar
include $(LEVEL)/Makefile.common

22
lib/Target/SparcV9/Makefile
View File

@ -1,4 +1,4 @@
##===- lib/Target/Sparc/Makefile ---------------------------*- Makefile -*-===##
##===- lib/Target/SparcV9/Makefile ---------------------------*- Makefile -*-===##
#
# The LLVM Compiler Infrastructure
#
@ -7,10 +7,10 @@
#
##===----------------------------------------------------------------------===##
LEVEL = ../../..
LIBRARYNAME = sparc
LIBRARYNAME = sparcv9
DIRS = InstrSelection RegAlloc LiveVar
ExtraSource = Sparc.burm.cpp
ExtraSource = SparcV9.burm.cpp
include $(LEVEL)/Makefile.common
@ -20,26 +20,26 @@ else
DEBUG_FLAG = -D_DEBUG
endif
Sparc.burg.in1 : $(SourceDir)/Sparc.burg.in
SparcV9.burg.in1 : $(SourceDir)/SparcV9.burg.in
$(CXX) -E -I$(LLVM_SRC_ROOT)/include $(DEBUG_FLAG) -x c++ $< | $(SED) '/^#/d' | $(SED) 's/Ydefine/#define/' > $@
Sparc.burm : Sparc.burg.in1
SparcV9.burm : SparcV9.burg.in1
$(CXX) -E -I$(LLVM_SRC_ROOT)/include $(DEBUG_FLAG) -x c++ $< | $(SED) '/^#/d' | $(SED) 's/^Xinclude/#include/' | $(SED) 's/^Xdefine/#define/' > $@
Sparc.burm.cpp: Sparc.burm
SparcV9.burm.cpp: SparcV9.burm
@echo "Burging `basename $<`"
$(RunBurg) $< -o $@
$(BUILD_OBJ_DIR)/Debug/Sparc.burm.lo: Sparc.burm.cpp
$(BUILD_OBJ_DIR)/Debug/SparcV9.burm.lo: SparcV9.burm.cpp
$(CompileG) $< -o $@
$(BUILD_OBJ_DIR)/Release/Sparc.burm.lo: Sparc.burm.cpp
$(BUILD_OBJ_DIR)/Release/SparcV9.burm.lo: SparcV9.burm.cpp
$(CompileO) $< -o $@
$(BUILD_OBJ_DIR)/Profile/Sparc.burm.lo: Sparc.burm.cpp
$(BUILD_OBJ_DIR)/Profile/SparcV9.burm.lo: SparcV9.burm.cpp
$(CompileP) $< -o $@
$(BUILD_OBJ_DIR)/Depend/Sparc.burm.d: $(BUILD_OBJ_DIR)/Depend/.dir
$(BUILD_OBJ_DIR)/Depend/SparcV9.burm.d: $(BUILD_OBJ_DIR)/Depend/.dir
touch $@
TARGET_NAME := SparcV9
@ -56,5 +56,5 @@ $(TARGET_NAME)CodeEmitter.inc:: $(SourceDir)/$(TARGET_NAME).td $(TABLEGEN_FILES)
$(TBLGEN) -I $(SourceDir) $< -gen-emitter -o $@
clean::
$(RM) -f $(TARGET_NAME)CodeEmitter.inc Sparc.burg.in1 Sparc.burm Sparc.burm.cpp
$(RM) -f $(TARGET_NAME)CodeEmitter.inc SparcV9.burg.in1 SparcV9.burm SparcV9.burm.cpp

2
lib/Target/SparcV9/MappingInfo.h
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@ -1,4 +1,4 @@
//===- lib/Target/Sparc/MappingInfo.h ---------------------------*- C++ -*-===//
//===- lib/Target/SparcV9/MappingInfo.h ---------------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/SparcV9/RegAlloc/Makefile
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@ -10,7 +10,7 @@ LEVEL = ../../../..
DIRS =
LIBRARYNAME = regalloc
LIBRARYNAME = sparcv9regalloc
BUILD_ARCHIVE = 1

2
lib/Target/SparcV9/SparcV9.burg.in
View File

@ -46,7 +46,7 @@ Xdefine PANIC printf
%term Or=OrOPCODE
%term Xor=XorOPCODE
/* Use the next 4 to distinguish bitwise operators from
* logical operators. This is no longer used for Sparc,
* logical operators. This is no longer used for SparcV9,
* but may be useful for other target machines.
* The last one is the bitwise Not(val) == XOR val, 11..1.
* Note that it is also a binary operator, not unary.

48
lib/Target/SparcV9/SparcV9.td
View File

@ -1,4 +1,4 @@
//===- SparcV9.td - Target Description for Sparc V9 Target ----------------===//
//===- SparcV9.td - Target Description for SparcV9 V9 Target ----------------===//
//
// The LLVM Compiler Infrastructure
//
@ -19,7 +19,7 @@ include "SparcV9_Reg.td"
// Instructions
//===----------------------------------------------------------------------===//
class InstV9 : Instruction { // Sparc instruction baseline
class InstV9 : Instruction { // SparcV9 instruction baseline
field bits<32> Inst;
let Namespace = "V9";
@ -27,7 +27,7 @@ class InstV9 : Instruction { // Sparc instruction baseline
bits<2> op;
let Inst{31-30} = op; // Top two bits are the 'op' field
// Bit attributes specific to Sparc instructions
// Bit attributes specific to SparcV9 instructions
bit isPasi = 0; // Does this instruction affect an alternate addr space?
bit isDeprecated = 0; // Is this instruction deprecated?
bit isPrivileged = 0; // Is this a privileged instruction?
@ -62,7 +62,7 @@ let op2 = 0b011 in {
}
// Section A.4: Branch on Floating-Point Condition Codes (FBfcc) p140
// The following deprecated instructions don't seem to play nice on Sparc
// The following deprecated instructions don't seem to play nice on SparcV9
/*
let isDeprecated = 1 in {
let op2 = 0b110 in {
@ -107,7 +107,7 @@ let op2 = 0b101 in {
}
// Section A.5: Branch on FP condition codes with prediction - p143
// Not used in the Sparc backend (directly)
// Not used in the SparcV9 backend (directly)
/*
let op2 = 0b101 in {
def FBPA : F2_3<0b1000, "fba">; // Branch always
@ -176,7 +176,7 @@ let op2 = 0b001 in {
}
// Section A.7: Branch on integer condition codes with prediction - p148
// Not used in the Sparc backend
// Not used in the SparcV9 backend
/*
let op2 = 0b001 in {
def BPA : F2_3<0b1000, "bpa">; // Branch always
@ -212,7 +212,7 @@ def CALL : InstV9 {
// Section A.10: Divide (64-bit / 32-bit) - p178
// Not used in the Sparc backend
// Not used in the SparcV9 backend
/*
let isDeprecated = 1 in {
def UDIVr : F3_1<2, 0b001110, "udiv">; // udiv r, r, r
@ -227,7 +227,7 @@ let isDeprecated = 1 in {
*/
// Section A.11: DONE and RETRY - p181
// Not used in the Sparc backend
// Not used in the SparcV9 backend
/*
let isPrivileged = 1 in {
def DONE : F3_18<0, "done">; // done
@ -247,7 +247,7 @@ def FSUBQ : F3_16<2, 0b110100, 0x47, "fsubq">; // fsubq frs1, frs2, frd
def FCMPS : F3_15<2, 0b110101, 0b001010001, "fcmps">; // fcmps %fcc, r1, r2
def FCMPD : F3_15<2, 0b110101, 0b001010010, "fcmpd">; // fcmpd %fcc, r1, r2
def FCMPQ : F3_15<2, 0b110101, 0b001010011, "fcmpq">; // fcmpq %fcc, r1, r2
// Currently unused in the Sparc backend
// Currently unused in the SparcV9 backend
/*
def FCMPES : F3_15<2, 0b110101, 0b001010101, "fcmpes">; // fcmpes %fcc, r1, r2
def FCMPED : F3_15<2, 0b110101, 0b001010110, "fcmped">; // fcmped %fcc, r1, r2
@ -317,7 +317,7 @@ def FSQRTQ : F3_14<2, 0b110100, 0b000101011, "fsqrts">; // fsqrts r, r
// Not currently used
// Section A.24: Jump and Link - p172
// Mimicking the Sparc's instr def...
// Mimicking the SparcV9's instr def...
def JMPLCALLr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
def JMPLCALLi : F3_2<2, 0b111000, "jmpl">; // jmpl [rs1+imm], rd
def JMPLRETr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
@ -393,7 +393,7 @@ def XNORccr : F3_1<2, 0b010111, "xnorcc">; // xnorcc rs1, rs2, rd
def XNORcci : F3_2<2, 0b010111, "xnorcc">; // xnorcc rs1, imm, rd
// Section A.32: Memory Barrier - p186
// Not currently used in the Sparc backend
// Not currently used in the SparcV9 backend
// Section A.33: Move Floating-Point Register on Condition (FMOVcc)
// ======================= Single Floating Point ======================
@ -622,7 +622,7 @@ def UDIVXr : F3_1<2, 0b001101, "udivx">; // udivx r, r, r
def UDIVXi : F3_2<2, 0b001101, "udivx">; // udivx r, i, r
// Section A.38: Multiply (32-bit) - p200
// Not used in the Sparc backend
// Not used in the SparcV9 backend
/*
let Inst{13} = 0 in {
def UMULr : F3_1<2, 0b001010, "umul">; // umul r, r, r
@ -639,7 +639,7 @@ let Inst{13} = 1 in {
*/
// Section A.39: Multiply Step - p202
// Not currently used in the Sparc backend
// Not currently used in the SparcV9 backend
// Section A.40: No operation - p204
// NOP is really a pseudo-instruction (special case of SETHI)
@ -652,13 +652,13 @@ let op2 = 0b100 in {
}
// Section A.41: Population Count - p205
// Not currently used in the Sparc backend
// Not currently used in the SparcV9 backend
// Section A.42: Prefetch Data - p206
// Not currently used in the Sparc backend
// Not currently used in the SparcV9 backend
// Section A.43: Read Privileged Register - p211
// Not currently used in the Sparc backend
// Not currently used in the SparcV9 backend
// Section A.44: Read State Register
// The only instr from this section currently used is RDCCR
@ -679,7 +679,7 @@ def RESTOREr : F3_1<2, 0b111101, "restore">; // restore r, r, r
def RESTOREi : F3_2<2, 0b111101, "restore">; // restore r, i, r
// Section A.47: SAVED and RESTORED - p219
// Not currently used in Sparc backend
// Not currently used in SparcV9 backend
// Section A.48: SETHI - p220
let op2 = 0b100 in {
@ -687,7 +687,7 @@ let op2 = 0b100 in {
}
// Section A.49: Shift - p221
// Not currently used in the Sparc backend
// Not currently used in the SparcV9 backend
/*
uses 5 least significant bits of rs2
let x = 0 in {
@ -720,10 +720,10 @@ def SRLXi6 : F3_13<2, 0b100110, "srlx">; // srlx r, shcnt64, r
def SRAXi6 : F3_13<2, 0b100111, "srax">; // srax r, shcnt64, r
// Section A.50: Sofware-Initiated Reset - p223
// Not currently used in the Sparc backend
// Not currently used in the SparcV9 backend
// Section A.51: Store Barrier - p224
// Not currently used in the Sparc backend
// Not currently used in the SparcV9 backend
// Section A.52: Store Floating-point - p225
// Store instructions all want their rd register first
@ -732,7 +732,7 @@ def STFi : F3_2rd<3, 0b100100, "st">; // st r, [r+i]
def STDFr : F3_1rd<3, 0b100111, "std">; // std r, [r+r]
def STDFi : F3_2rd<3, 0b100111, "std">; // std r, [r+i]
// Not currently used in the Sparc backend
// Not currently used in the SparcV9 backend
/*
def STQFr : F3_1rd<3, 0b100110, "stq">; // stq r, [r+r]
def STQFi : F3_2rd<3, 0b100110, "stq">; // stq r, [r+i]
@ -740,7 +740,7 @@ def STQFi : F3_2rd<3, 0b100110, "stq">; // stq r, [r+i]
// FIXME: An encoding needs to be chosen here, because STFSRx expect rd=0,
// while STXFSRx expect rd=1, but assembly syntax dictates %fsr as first arg.
// These are being disabled because they aren't used in the Sparc backend.
// These are being disabled because they aren't used in the SparcV9 backend.
/*
let isDeprecated = 1 in {
def STFSRr : F3_1<3, 0b100101, "st">; // st %fsr, [r+r]
@ -751,7 +751,7 @@ def STXFSRr : F3_1<3, 0b100101, "stx">; // stx %fsr, [r+r]
def STXFSRi : F3_2<3, 0b100101, "stx">; // stx %fsr, [r+i]
// Section A.53: Store Floating-Point into Alternate Space - p227
// Not currently used in the Sparc backend
// Not currently used in the SparcV9 backend
// Section A.54: Store Integer - p229
// Store instructions all want their rd register first
@ -765,7 +765,7 @@ def STXr : F3_1rd<3, 0b001110, "stx">; // stx r, [r+r]
def STXi : F3_2rd<3, 0b001110, "stx">; // stx r, [r+i]
// Section A.55: Store Integer into Alternate Space - p231
// Not currently used in the Sparc backend
// Not currently used in the SparcV9 backend
// Section A.56: Subtract - p233
def SUBr : F3_1<2, 0b000100, "sub">; // sub r, r, r

38
lib/Target/SparcV9/SparcV9AsmPrinter.cpp
View File

@ -1,4 +1,4 @@
//===-- EmitAssembly.cpp - Emit Sparc Specific .s File ---------------------==//
//===-- EmitAssembly.cpp - Emit SparcV9 Specific .s File ---------------------==//
//
// The LLVM Compiler Infrastructure
//
@ -30,7 +30,7 @@
#include "llvm/Support/Mangler.h"
#include "Support/StringExtras.h"
#include "Support/Statistic.h"
#include "SparcInternals.h"
#include "SparcV9Internals.h"
#include <string>
using namespace llvm;
@ -251,7 +251,7 @@ namespace {
}
// getID Wrappers - Ensure consistent usage
// Symbol names in Sparc assembly language have these rules:
// Symbol names in SparcV9 assembly language have these rules:
// (a) Must match { letter | _ | . | $ } { letter | _ | . | $ | digit }*
// (b) A name beginning in "." is treated as a local name.
std::string getID(const Function *F) {
@ -504,19 +504,19 @@ std::string AsmPrinter::valToExprString(const Value* V,
//===----------------------------------------------------------------------===//
// SparcAsmPrinter Code
// SparcV9AsmPrinter Code
//===----------------------------------------------------------------------===//
namespace {
struct SparcAsmPrinter : public FunctionPass, public AsmPrinter {
inline SparcAsmPrinter(std::ostream &os, const TargetMachine &t)
struct SparcV9AsmPrinter : public FunctionPass, public AsmPrinter {
inline SparcV9AsmPrinter(std::ostream &os, const TargetMachine &t)
: AsmPrinter(os, t) {}
const Function *currFunction;
const char *getPassName() const {
return "Output Sparc Assembly for Functions";
return "Output SparcV9 Assembly for Functions";
}
virtual bool doInitialization(Module &M) {
@ -565,7 +565,7 @@ namespace {
} // End anonymous namespace
inline bool
SparcAsmPrinter::OpIsBranchTargetLabel(const MachineInstr *MI,
SparcV9AsmPrinter::OpIsBranchTargetLabel(const MachineInstr *MI,
unsigned int opNum) {
switch (MI->getOpcode()) {
case V9::JMPLCALLr:
@ -579,7 +579,7 @@ SparcAsmPrinter::OpIsBranchTargetLabel(const MachineInstr *MI,
}
inline bool
SparcAsmPrinter::OpIsMemoryAddressBase(const MachineInstr *MI,
SparcV9AsmPrinter::OpIsMemoryAddressBase(const MachineInstr *MI,
unsigned int opNum) {
if (Target.getInstrInfo().isLoad(MI->getOpcode()))
return (opNum == 0);
@ -596,7 +596,7 @@ SparcAsmPrinter::OpIsMemoryAddressBase(const MachineInstr *MI,
printOneOperand(mop2, opCode);
unsigned int
SparcAsmPrinter::printOperands(const MachineInstr *MI,
SparcV9AsmPrinter::printOperands(const MachineInstr *MI,
unsigned int opNum)
{
const MachineOperand& mop = MI->getOperand(opNum);
@ -616,7 +616,7 @@ SparcAsmPrinter::printOperands(const MachineInstr *MI,
}
void
SparcAsmPrinter::printOneOperand(const MachineOperand &mop,
SparcV9AsmPrinter::printOneOperand(const MachineOperand &mop,
MachineOpCode opCode)
{
bool needBitsFlag = true;
@ -659,7 +659,7 @@ SparcAsmPrinter::printOneOperand(const MachineOperand &mop,
case MachineOperand::MO_PCRelativeDisp:
{
const Value *Val = mop.getVRegValue();
assert(Val && "\tNULL Value in SparcAsmPrinter");
assert(Val && "\tNULL Value in SparcV9AsmPrinter");
if (const BasicBlock *BB = dyn_cast<BasicBlock>(Val))
toAsm << getID(BB);
@ -670,7 +670,7 @@ SparcAsmPrinter::printOneOperand(const MachineOperand &mop,
else if (const Constant *CV = dyn_cast<Constant>(Val))
toAsm << getID(CV);
else
assert(0 && "Unrecognized value in SparcAsmPrinter");
assert(0 && "Unrecognized value in SparcV9AsmPrinter");
break;
}
@ -691,7 +691,7 @@ SparcAsmPrinter::printOneOperand(const MachineOperand &mop,
toAsm << ")";
}
void SparcAsmPrinter::emitMachineInst(const MachineInstr *MI) {
void SparcV9AsmPrinter::emitMachineInst(const MachineInstr *MI) {
unsigned Opcode = MI->getOpcode();
if (Target.getInstrInfo().isDummyPhiInstr(Opcode))
@ -715,7 +715,7 @@ void SparcAsmPrinter::emitMachineInst(const MachineInstr *MI) {
++EmittedInsts;
}
void SparcAsmPrinter::emitBasicBlock(const MachineBasicBlock &MBB) {
void SparcV9AsmPrinter::emitBasicBlock(const MachineBasicBlock &MBB) {
// Emit a label for the basic block
toAsm << getID(MBB.getBasicBlock()) << ":\n";
@ -726,7 +726,7 @@ void SparcAsmPrinter::emitBasicBlock(const MachineBasicBlock &MBB) {
toAsm << "\n"; // Separate BB's with newlines
}
void SparcAsmPrinter::emitFunction(const Function &F) {
void SparcV9AsmPrinter::emitFunction(const Function &F) {
std::string methName = getID(&F);
toAsm << "!****** Outputing Function: " << methName << " ******\n";
@ -760,7 +760,7 @@ void SparcAsmPrinter::emitFunction(const Function &F) {
toAsm << "\n\n";
}
void SparcAsmPrinter::printGlobalVariable(const GlobalVariable* GV) {
void SparcV9AsmPrinter::printGlobalVariable(const GlobalVariable* GV) {
if (GV->hasExternalLinkage())
toAsm << "\t.global\t" << getID(GV) << "\n";
@ -776,7 +776,7 @@ void SparcAsmPrinter::printGlobalVariable(const GlobalVariable* GV) {
}
}
void SparcAsmPrinter::emitGlobals(const Module &M) {
void SparcV9AsmPrinter::emitGlobals(const Module &M) {
// Output global variables...
for (Module::const_giterator GI = M.gbegin(), GE = M.gend(); GI != GE; ++GI)
if (! GI->isExternal()) {
@ -796,5 +796,5 @@ void SparcAsmPrinter::emitGlobals(const Module &M) {
FunctionPass *llvm::createAsmPrinterPass(std::ostream &Out,
const TargetMachine &TM) {
return new SparcAsmPrinter(Out, TM);
return new SparcV9AsmPrinter(Out, TM);
}

58
lib/Target/SparcV9/SparcV9CodeEmitter.cpp
View File

@ -34,9 +34,9 @@
#include "Support/Debug.h"
#include "Support/hash_set"
#include "Support/Statistic.h"
#include "SparcInternals.h"
#include "SparcTargetMachine.h"
#include "SparcRegInfo.h"
#include "SparcV9Internals.h"
#include "SparcV9TargetMachine.h"
#include "SparcV9RegInfo.h"
#include "SparcV9CodeEmitter.h"
#include "Config/alloca.h"
@ -48,12 +48,12 @@ namespace {
Statistic<> CallbackCalls("callback", "Number CompilationCallback() calls");
}
bool SparcTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
bool SparcV9TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
MachineCodeEmitter &MCE) {
MachineCodeEmitter *M = &MCE;
DEBUG(M = MachineCodeEmitter::createFilePrinterEmitter(MCE));
PM.add(new SparcV9CodeEmitter(*this, *M));
PM.add(createSparcMachineCodeDestructionPass()); //Free stuff no longer needed
PM.add(createSparcV9MachineCodeDestructionPass()); //Free stuff no longer needed
return false;
}
@ -179,8 +179,8 @@ void JITResolver::insertJumpAtAddr(int64_t JumpTarget, uint64_t &Addr) {
void JITResolver::insertFarJumpAtAddr(int64_t Target, uint64_t Addr) {
static const unsigned
o6 = SparcIntRegClass::o6, g0 = SparcIntRegClass::g0,
g1 = SparcIntRegClass::g1, g5 = SparcIntRegClass::g5;
o6 = SparcV9IntRegClass::o6, g0 = SparcV9IntRegClass::g0,
g1 = SparcV9IntRegClass::g1, g5 = SparcV9IntRegClass::g5;
MachineInstr* BinaryCode[] = {
//
@ -362,7 +362,7 @@ void JITResolver::CompilationCallback() {
// Rewrite the call target so that we don't fault every time we execute it.
//
static const unsigned o6 = SparcIntRegClass::o6;
static const unsigned o6 = SparcV9IntRegClass::o6;
// Subtract enough to overwrite up to the 'save' instruction
// This depends on whether we made a short call (1 instruction) or the
@ -418,7 +418,7 @@ uint64_t JITResolver::emitStubForFunction(Function *F) {
DEBUG(std::cerr << "Emitting stub at addr: 0x"
<< std::hex << MCE.getCurrentPCValue() << "\n");
unsigned o6 = SparcIntRegClass::o6, g0 = SparcIntRegClass::g0;
unsigned o6 = SparcV9IntRegClass::o6, g0 = SparcV9IntRegClass::g0;
// restore %g0, 0, %g0
MachineInstr *R = BuildMI(V9::RESTOREi, 3).addMReg(g0).addSImm(0)
@ -485,8 +485,8 @@ SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg,
fakeReg = RI.getClassRegNum(fakeReg, regClass);
switch (regClass) {
case SparcRegInfo::IntRegClassID: {
// Sparc manual, p31
case SparcV9RegInfo::IntRegClassID: {
// SparcV9 manual, p31
static const unsigned IntRegMap[] = {
// "o0", "o1", "o2", "o3", "o4", "o5", "o7",
8, 9, 10, 11, 12, 13, 15,
@ -503,14 +503,14 @@ SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg,
return IntRegMap[fakeReg];
break;
}
case SparcRegInfo::FloatRegClassID: {
case SparcV9RegInfo::FloatRegClassID: {
DEBUG(std::cerr << "FP reg: " << fakeReg << "\n");
if (regType == SparcRegInfo::FPSingleRegType) {
if (regType == SparcV9RegInfo::FPSingleRegType) {
// only numbered 0-31, hence can already fit into 5 bits (and 6)
DEBUG(std::cerr << "FP single reg, returning: " << fakeReg << "\n");
} else if (regType == SparcRegInfo::FPDoubleRegType) {
} else if (regType == SparcV9RegInfo::FPDoubleRegType) {
// FIXME: This assumes that we only have 5-bit register fields!
// From Sparc Manual, page 40.
// From SparcV9 Manual, page 40.
// The bit layout becomes: b[4], b[3], b[2], b[1], b[5]
fakeReg |= (fakeReg >> 5) & 1;
fakeReg &= 0x1f;
@ -518,7 +518,7 @@ SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg,
}
return fakeReg;
}
case SparcRegInfo::IntCCRegClassID: {
case SparcV9RegInfo::IntCCRegClassID: {
/* xcc, icc, ccr */
static const unsigned IntCCReg[] = { 6, 4, 2 };
@ -527,7 +527,7 @@ SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg,
DEBUG(std::cerr << "IntCC reg: " << IntCCReg[fakeReg] << "\n");
return IntCCReg[fakeReg];
}
case SparcRegInfo::FloatCCRegClassID: {
case SparcV9RegInfo::FloatCCRegClassID: {
/* These are laid out %fcc0 - %fcc3 => 0 - 3, so are correct */
DEBUG(std::cerr << "FP CC reg: " << fakeReg << "\n");
return fakeReg;
@ -542,9 +542,9 @@ SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg,
// WARNING: if the call used the delay slot to do meaningful work, that's not
// being accounted for, and the behavior will be incorrect!!
inline void SparcV9CodeEmitter::emitFarCall(uint64_t Target, Function *F) {
static const unsigned o6 = SparcIntRegClass::o6,
o7 = SparcIntRegClass::o7, g0 = SparcIntRegClass::g0,
g1 = SparcIntRegClass::g1, g5 = SparcIntRegClass::g5;
static const unsigned o6 = SparcV9IntRegClass::o6,
o7 = SparcV9IntRegClass::o7, g0 = SparcV9IntRegClass::g0,
g1 = SparcV9IntRegClass::g1, g5 = SparcV9IntRegClass::g5;
MachineInstr* BinaryCode[] = {
//
@ -582,7 +582,7 @@ inline void SparcV9CodeEmitter::emitFarCall(uint64_t Target, Function *F) {
}
}
void SparcJITInfo::replaceMachineCodeForFunction (void *Old, void *New) {
void SparcV9JITInfo::replaceMachineCodeForFunction (void *Old, void *New) {
assert (TheJITResolver &&
"Can only call replaceMachineCodeForFunction from within JIT");
uint64_t Target = (uint64_t)(intptr_t)New;
@ -658,7 +658,7 @@ int64_t SparcV9CodeEmitter::getMachineOpValue(MachineInstr &MI,
}
} else if (MO.isRegister() || MO.getType() == MachineOperand::MO_CCRegister)
{
// This is necessary because the Sparc backend doesn't actually lay out
// This is necessary because the SparcV9 backend doesn't actually lay out
// registers in the real fashion -- it skips those that it chooses not to
// allocate, i.e. those that are the FP, SP, etc.
unsigned fakeReg = MO.getReg();
@ -677,17 +677,17 @@ int64_t SparcV9CodeEmitter::getMachineOpValue(MachineInstr &MI,
MI, MO.isPCRelative());
} else if (MO.isMachineBasicBlock()) {
// Duplicate code of the above case for VirtualRegister, BasicBlock...
// It should really hit this case, but Sparc backend uses VRegs instead
// It should really hit this case, but SparcV9 backend uses VRegs instead
DEBUG(std::cerr << "Saving reference to MBB\n");
const BasicBlock *BB = MO.getMachineBasicBlock()->getBasicBlock();
unsigned* CurrPC = (unsigned*)(intptr_t)MCE.getCurrentPCValue();
BBRefs.push_back(std::make_pair(BB, std::make_pair(CurrPC, &MI)));
} else if (MO.isExternalSymbol()) {
// Sparc backend doesn't generate this (yet...)
// SparcV9 backend doesn't generate this (yet...)
std::cerr << "ERROR: External symbol unhandled: " << MO << "\n";
abort();
} else if (MO.isFrameIndex()) {
// Sparc backend doesn't generate this (yet...)
// SparcV9 backend doesn't generate this (yet...)
int FrameIndex = MO.getFrameIndex();
std::cerr << "ERROR: Frame index unhandled.\n";
abort();
@ -703,13 +703,13 @@ int64_t SparcV9CodeEmitter::getMachineOpValue(MachineInstr &MI,
// are used in SPARC assembly. (Some of these make no sense in combination
// with some of the above; we'll trust that the instruction selector
// will not produce nonsense, and not check for valid combinations here.)
if (MO.isLoBits32()) { // %lo(val) == %lo() in Sparc ABI doc
if (MO.isLoBits32()) { // %lo(val) == %lo() in SparcV9 ABI doc
return rv & 0x03ff;
} else if (MO.isHiBits32()) { // %lm(val) == %hi() in Sparc ABI doc
} else if (MO.isHiBits32()) { // %lm(val) == %hi() in SparcV9 ABI doc
return (rv >> 10) & 0x03fffff;
} else if (MO.isLoBits64()) { // %hm(val) == %ulo() in Sparc ABI doc
} else if (MO.isLoBits64()) { // %hm(val) == %ulo() in SparcV9 ABI doc
return (rv >> 32) & 0x03ff;
} else if (MO.isHiBits64()) { // %hh(val) == %uhi() in Sparc ABI doc
} else if (MO.isHiBits64()) { // %hh(val) == %uhi() in SparcV9 ABI doc
return rv >> 42;
} else { // (unadorned) val
return rv;

12
lib/Target/SparcV9/SparcV9FrameInfo.cpp
View File

@ -1,4 +1,4 @@
//===-- Sparc.cpp - General implementation file for the Sparc Target ------===//
//===-- SparcV9.cpp - General implementation file for the SparcV9 Target ------===//
//
// The LLVM Compiler Infrastructure
//
@ -16,18 +16,18 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionInfo.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "SparcFrameInfo.h"
#include "SparcV9FrameInfo.h"
using namespace llvm;
int
SparcFrameInfo::getFirstAutomaticVarOffset(MachineFunction&, bool& pos) const {
SparcV9FrameInfo::getFirstAutomaticVarOffset(MachineFunction&, bool& pos) const {
pos = false; // static stack area grows downwards
return StaticAreaOffsetFromFP;
}
int
SparcFrameInfo::getRegSpillAreaOffset(MachineFunction& mcInfo, bool& pos) const
SparcV9FrameInfo::getRegSpillAreaOffset(MachineFunction& mcInfo, bool& pos) const
{
// ensure no more auto vars are added
mcInfo.getInfo()->freezeAutomaticVarsArea();
@ -37,7 +37,7 @@ SparcFrameInfo::getRegSpillAreaOffset(MachineFunction& mcInfo, bool& pos) const
return StaticAreaOffsetFromFP - autoVarsSize;
}
int SparcFrameInfo::getTmpAreaOffset(MachineFunction& mcInfo, bool& pos) const {
int SparcV9FrameInfo::getTmpAreaOffset(MachineFunction& mcInfo, bool& pos) const {
MachineFunctionInfo *MFI = mcInfo.getInfo();
MFI->freezeAutomaticVarsArea(); // ensure no more auto vars are added
MFI->freezeSpillsArea(); // ensure no more spill slots are added
@ -50,7 +50,7 @@ int SparcFrameInfo::getTmpAreaOffset(MachineFunction& mcInfo, bool& pos) const {
}
int
SparcFrameInfo::getDynamicAreaOffset(MachineFunction& mcInfo, bool& pos) const {
SparcV9FrameInfo::getDynamicAreaOffset(MachineFunction& mcInfo, bool& pos) const {
// Dynamic stack area grows downwards starting at top of opt-args area.
// The opt-args, required-args, and register-save areas are empty except
// during calls and traps, so they are shifted downwards on each

12
lib/Target/SparcV9/SparcV9FrameInfo.h
View File

@ -1,4 +1,4 @@
//===-- SparcFrameInfo.h - Define TargetFrameInfo for Sparc -----*- C++ -*-===//
//===-- SparcV9FrameInfo.h - Define TargetFrameInfo for SparcV9 -----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -22,10 +22,10 @@
namespace llvm {
class SparcFrameInfo: public TargetFrameInfo {
class SparcV9FrameInfo: public TargetFrameInfo {
const TargetMachine &target;
public:
SparcFrameInfo(const TargetMachine &TM)
SparcV9FrameInfo(const TargetMachine &TM)
: TargetFrameInfo(StackGrowsDown, StackFrameSizeAlignment, 0), target(TM) {}
public:
@ -114,10 +114,10 @@ public:
private:
/*----------------------------------------------------------------------
This diagram shows the stack frame layout used by llc on Sparc V9.
This diagram shows the stack frame layout used by llc on SparcV9 V9.
Note that only the location of automatic variables, spill area,
temporary storage, and dynamically allocated stack area are chosen
by us. The rest conform to the Sparc V9 ABI.
by us. The rest conform to the SparcV9 V9 ABI.
All stack addresses are offset by OFFSET = 0x7ff (2047).
Alignment assumptions and other invariants:
@ -156,7 +156,7 @@ private:
*----------------------------------------------------------------------*/
// All stack addresses must be offset by 0x7ff (2047) on Sparc V9.
// All stack addresses must be offset by 0x7ff (2047) on SparcV9 V9.
static const int OFFSET = (int) 0x7ff;
static const int StackFrameSizeAlignment = 16;
static const int MinStackFrameSize = 176;

34
lib/Target/SparcV9/SparcV9InstrInfo.cpp
View File

@ -1,4 +1,4 @@
//===-- SparcInstrInfo.cpp ------------------------------------------------===//
//===-- SparcV9InstrInfo.cpp ------------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@ -20,9 +20,9 @@
#include "llvm/CodeGen/MachineFunctionInfo.h"
#include "llvm/CodeGen/MachineCodeForInstruction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "SparcInternals.h"
#include "SparcInstrSelectionSupport.h"
#include "SparcInstrInfo.h"
#include "SparcV9Internals.h"
#include "SparcV9InstrSelectionSupport.h"
#include "SparcV9InstrInfo.h"
namespace llvm {
@ -42,7 +42,7 @@ static const uint32_t MAXSIMM = (1 << 12) - 1; // set bits in simm13 field of OR
//---------------------------------------------------------------------------
uint64_t
SparcInstrInfo::ConvertConstantToIntType(const TargetMachine &target,
SparcV9InstrInfo::ConvertConstantToIntType(const TargetMachine &target,
const Value *V,
const Type *destType,
bool &isValidConstant) const
@ -386,7 +386,7 @@ MaxConstantForInstr(unsigned llvmOpCode)
default: break;
};
return (modelOpCode < 0)? 0: SparcMachineInstrDesc[modelOpCode].maxImmedConst;
return (modelOpCode < 0)? 0: SparcV9MachineInstrDesc[modelOpCode].maxImmedConst;
}
static void
@ -407,18 +407,18 @@ InitializeMaxConstantsTable()
//---------------------------------------------------------------------------
// class SparcInstrInfo
// class SparcV9InstrInfo
//
// Purpose:
// Information about individual instructions.
// Most information is stored in the SparcMachineInstrDesc array above.
// Most information is stored in the SparcV9MachineInstrDesc array above.
// Other information is computed on demand, and most such functions
// default to member functions in base class TargetInstrInfo.
//---------------------------------------------------------------------------
/*ctor*/
SparcInstrInfo::SparcInstrInfo()
: TargetInstrInfo(SparcMachineInstrDesc,
SparcV9InstrInfo::SparcV9InstrInfo()
: TargetInstrInfo(SparcV9MachineInstrDesc,
/*descSize = */ V9::NUM_TOTAL_OPCODES,
/*numRealOpCodes = */ V9::NUM_REAL_OPCODES)
{
@ -426,7 +426,7 @@ SparcInstrInfo::SparcInstrInfo()
}
bool
SparcInstrInfo::ConstantMayNotFitInImmedField(const Constant* CV,
SparcV9InstrInfo::ConstantMayNotFitInImmedField(const Constant* CV,
const Instruction* I) const
{
if (I->getOpcode() >= MaxConstantsTable.size()) // user-defined op (or bug!)
@ -456,7 +456,7 @@ SparcInstrInfo::ConstantMayNotFitInImmedField(const Constant* CV,
// Any stack space required is allocated via MachineFunction.
//
void
SparcInstrInfo::CreateCodeToLoadConst(const TargetMachine& target,
SparcV9InstrInfo::CreateCodeToLoadConst(const TargetMachine& target,
Function* F,
Value* val,
Instruction* dest,
@ -553,7 +553,7 @@ SparcInstrInfo::CreateCodeToLoadConst(const TargetMachine& target,
// Any stack space required is allocated via MachineFunction.
//
void
SparcInstrInfo::CreateCodeToCopyIntToFloat(const TargetMachine& target,
SparcV9InstrInfo::CreateCodeToCopyIntToFloat(const TargetMachine& target,
Function* F,
Value* val,
Instruction* dest,
@ -614,7 +614,7 @@ SparcInstrInfo::CreateCodeToCopyIntToFloat(const TargetMachine& target,
// Temporary stack space required is allocated via MachineFunction.
//
void
SparcInstrInfo::CreateCodeToCopyFloatToInt(const TargetMachine& target,
SparcV9InstrInfo::CreateCodeToCopyFloatToInt(const TargetMachine& target,
Function* F,
Value* val,
Instruction* dest,
@ -665,7 +665,7 @@ SparcInstrInfo::CreateCodeToCopyFloatToInt(const TargetMachine& target,
// Any stack space required is allocated via MachineFunction.
//
void
SparcInstrInfo::CreateCopyInstructionsByType(const TargetMachine& target,
SparcV9InstrInfo::CreateCopyInstructionsByType(const TargetMachine& target,
Function *F,
Value* src,
Instruction* dest,
@ -761,7 +761,7 @@ CreateBitExtensionInstructions(bool signExtend,
// Any stack space required is allocated via MachineFunction.
//
void
SparcInstrInfo::CreateSignExtensionInstructions(
SparcV9InstrInfo::CreateSignExtensionInstructions(
const TargetMachine& target,
Function* F,
Value* srcVal,
@ -783,7 +783,7 @@ SparcInstrInfo::CreateSignExtensionInstructions(
// Any stack space required is allocated via MachineFunction.
//
void
SparcInstrInfo::CreateZeroExtensionInstructions(
SparcV9InstrInfo::CreateZeroExtensionInstructions(
const TargetMachine& target,
Function* F,
Value* srcVal,

14
lib/Target/SparcV9/SparcV9InstrInfo.h
View File

@ -1,4 +1,4 @@
//===-- SparcInstrInfo.h - Define TargetInstrInfo for Sparc -----*- C++ -*-===//
//===-- SparcV9InstrInfo.h - Define TargetInstrInfo for SparcV9 -----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -8,7 +8,7 @@
//===----------------------------------------------------------------------===//
//
// This class contains information about individual instructions.
// Most information is stored in the SparcMachineInstrDesc array above.
// Most information is stored in the SparcV9MachineInstrDesc array above.
// Other information is computed on demand, and most such functions
// default to member functions in base class TargetInstrInfo.
//
@ -19,12 +19,12 @@
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "SparcInternals.h"
#include "SparcV9Internals.h"
namespace llvm {
struct SparcInstrInfo : public TargetInstrInfo {
SparcInstrInfo();
struct SparcV9InstrInfo : public TargetInstrInfo {
SparcV9InstrInfo();
// All immediate constants are in position 1 except the
// store instructions and SETxx.
@ -53,7 +53,7 @@ struct SparcInstrInfo : public TargetInstrInfo {
/// another instruction, e.g. X86: xchg ax, ax; SparcV9: sethi 0, g0
///
MachineInstr* createNOPinstr() const {
return BuildMI(V9::SETHI, 2).addZImm(0).addReg(SparcIntRegClass::g0);
return BuildMI(V9::SETHI, 2).addZImm(0).addReg(SparcV9IntRegClass::g0);
}
/// isNOPinstr - not having a special NOP opcode, we need to know if a given
@ -66,7 +66,7 @@ struct SparcInstrInfo : public TargetInstrInfo {
const MachineOperand &op0 = MI.getOperand(0), &op1 = MI.getOperand(1);
if (op0.isImmediate() && op0.getImmedValue() == 0 &&
op1.getType() == MachineOperand::MO_MachineRegister &&
op1.getMachineRegNum() == SparcIntRegClass::g0)
op1.getMachineRegNum() == SparcV9IntRegClass::g0)
{
return true;
}

28
lib/Target/SparcV9/SparcV9InstrSelection.cpp
View File

@ -1,4 +1,4 @@
//===-- SparcInstrSelection.cpp -------------------------------------------===//
//===-- SparcV9InstrSelection.cpp -------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@ -24,10 +24,10 @@
#include "llvm/CodeGen/MachineFunctionInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineInstrAnnot.h"
#include "SparcInstrSelectionSupport.h"
#include "SparcInternals.h"
#include "SparcRegClassInfo.h"
#include "SparcRegInfo.h"
#include "SparcV9InstrSelectionSupport.h"
#include "SparcV9Internals.h"
#include "SparcV9RegClassInfo.h"
#include "SparcV9RegInfo.h"
#include "Support/MathExtras.h"
#include <algorithm>
#include <cmath>
@ -1413,7 +1413,7 @@ static bool CodeGenIntrinsic(Intrinsic::ID iid, CallInst &callInstr,
}
case Intrinsic::va_end:
return true; // no-op on Sparc
return true; // no-op on SparcV9
case Intrinsic::va_copy:
// Simple copy of current va_list (arg1) to new va_list (result)
@ -1543,13 +1543,13 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
// -- For non-FP values, create an add-with-0 instruction
//
if (retVal != NULL) {
const SparcRegInfo& regInfo =
(SparcRegInfo&) target.getRegInfo();
const SparcV9RegInfo& regInfo =
(SparcV9RegInfo&) target.getRegInfo();
const Type* retType = retVal->getType();
unsigned regClassID = regInfo.getRegClassIDOfType(retType);
unsigned retRegNum = (retType->isFloatingPoint()
? (unsigned) SparcFloatRegClass::f0
: (unsigned) SparcIntRegClass::i0);
? (unsigned) SparcV9FloatRegClass::f0
: (unsigned) SparcV9IntRegClass::i0);
retRegNum = regInfo.getUnifiedRegNum(regClassID, retRegNum);
// () Insert sign-extension instructions for small signed values.
@ -2450,8 +2450,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
MachineFunction& MF = MachineFunction::get(currentFunc);
MachineCodeForInstruction& mcfi =
MachineCodeForInstruction::get(callInstr);
const SparcRegInfo& regInfo =
(SparcRegInfo&) target.getRegInfo();
const SparcV9RegInfo& regInfo =
(SparcV9RegInfo&) target.getRegInfo();
const TargetFrameInfo& frameInfo = target.getFrameInfo();
// Create hidden virtual register for return address with type void*
@ -2701,8 +2701,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
const Type* retType = callInstr->getType();
int regNum = (retType->isFloatingPoint()
? (unsigned) SparcFloatRegClass::f0
: (unsigned) SparcIntRegClass::o0);
? (unsigned) SparcV9FloatRegClass::f0
: (unsigned) SparcV9IntRegClass::o0);
unsigned regClassID = regInfo.getRegClassIDOfType(retType);
regNum = regInfo.getUnifiedRegNum(regClassID, regNum);

6
lib/Target/SparcV9/SparcV9InstrSelectionSupport.h
View File

@ -1,4 +1,4 @@
//===-- llvm/CodeGen/SparcInstrSelectionSupport.h ---------------*- C++ -*-===//
//===-- llvm/CodeGen/SparcV9InstrSelectionSupport.h ---------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -15,7 +15,7 @@
#define SPARC_INSTR_SELECTION_SUPPORT_h
#include "llvm/DerivedTypes.h"
#include "SparcInternals.h"
#include "SparcV9Internals.h"
namespace llvm {
@ -90,7 +90,7 @@ ChooseAddInstructionByType(const Type* resultType)
}
// Because the Sparc instruction selector likes to re-write operands to
// Because the SparcV9 instruction selector likes to re-write operands to
// instructions, making them change from a Value* (virtual register) to a
// Constant* (making an immediate field), we need to change the opcode from a
// register-based instruction to an immediate-based instruction, hence this

36
lib/Target/SparcV9/SparcV9Internals.h
View File

@ -1,4 +1,4 @@
//===-- SparcInternals.h ----------------------------------------*- C++ -*-===//
//===-- SparcV9Internals.h ----------------------------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -7,7 +7,7 @@
//
//===----------------------------------------------------------------------===//
//
// This file defines stuff that is to be private to the Sparc backend, but is
// This file defines stuff that is to be private to the SparcV9 backend, but is
// shared among different portions of the backend.
//
//===----------------------------------------------------------------------===//
@ -22,16 +22,16 @@
#include "llvm/Target/TargetCacheInfo.h"
#include "llvm/Target/TargetRegInfo.h"
#include "llvm/Type.h"
#include "SparcRegClassInfo.h"
#include "SparcV9RegClassInfo.h"
#include "Config/sys/types.h"
namespace llvm {
class LiveRange;
class SparcTargetMachine;
class SparcV9TargetMachine;
class Pass;
enum SparcInstrSchedClass {
enum SparcV9InstrSchedClass {
SPARC_NONE, /* Instructions with no scheduling restrictions */
SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */
SPARC_IEU0, /* Integer class IEU0 */
@ -49,20 +49,20 @@ enum SparcInstrSchedClass {
//---------------------------------------------------------------------------
// enum SparcMachineOpCode.
// const TargetInstrDescriptor SparcMachineInstrDesc[]
// enum SparcV9MachineOpCode.
// const TargetInstrDescriptor SparcV9MachineInstrDesc[]
//
// Purpose:
// Description of UltraSparc machine instructions.
// Description of UltraSparcV9 machine instructions.
//
//---------------------------------------------------------------------------
namespace V9 {
enum SparcMachineOpCode {
enum SparcV9MachineOpCode {
#define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
ENUM,
#include "SparcInstr.def"
#include "SparcV9Instr.def"
// End-of-array marker
INVALID_OPCODE,
@ -72,33 +72,33 @@ namespace V9 {
}
// Array of machine instruction descriptions...
extern const TargetInstrDescriptor SparcMachineInstrDesc[];
extern const TargetInstrDescriptor SparcV9MachineInstrDesc[];
//---------------------------------------------------------------------------
// class SparcSchedInfo
// class SparcV9SchedInfo
//
// Purpose:
// Interface to instruction scheduling information for UltraSPARC.
// The parameter values above are based on UltraSPARC IIi.
//---------------------------------------------------------------------------
class SparcSchedInfo: public TargetSchedInfo {
class SparcV9SchedInfo: public TargetSchedInfo {
public:
SparcSchedInfo(const TargetMachine &tgt);
SparcV9SchedInfo(const TargetMachine &tgt);
protected:
virtual void initializeResources();
};
//---------------------------------------------------------------------------
// class SparcCacheInfo
// class SparcV9CacheInfo
//
// Purpose:
// Interface to cache parameters for the UltraSPARC.
// Just use defaults for now.
//---------------------------------------------------------------------------
struct SparcCacheInfo: public TargetCacheInfo {
SparcCacheInfo(const TargetMachine &T) : TargetCacheInfo(T) {}
struct SparcV9CacheInfo: public TargetCacheInfo {
SparcV9CacheInfo(const TargetMachine &T) : TargetCacheInfo(T) {}
};
@ -127,7 +127,7 @@ FunctionPass* createPrologEpilogInsertionPass();
///
Pass* createBytecodeAsmPrinterPass(std::ostream &Out);
FunctionPass *createSparcMachineCodeDestructionPass();
FunctionPass *createSparcV9MachineCodeDestructionPass();
} // End llvm namespace

8
lib/Target/SparcV9/SparcV9JITInfo.h
View File

@ -1,4 +1,4 @@
//===- SparcJITInfo.h - Sparc implementation of the JIT interface -*-C++-*-===//
//===- SparcV9JITInfo.h - SparcV9 implementation of the JIT interface -*-C++-*-===//
//
// The LLVM Compiler Infrastructure
//
@ -7,7 +7,7 @@
//
//===----------------------------------------------------------------------===//
//
// This file contains the Sparc implementation of the TargetJITInfo class.
// This file contains the SparcV9 implementation of the TargetJITInfo class.
//
//===----------------------------------------------------------------------===//
@ -19,10 +19,10 @@
namespace llvm {
class TargetMachine;
class SparcJITInfo : public TargetJITInfo {
class SparcV9JITInfo : public TargetJITInfo {
TargetMachine &TM;
public:
SparcJITInfo(TargetMachine &tm) : TM(tm) {}
SparcV9JITInfo(TargetMachine &tm) : TM(tm) {}
/// addPassesToJITCompile - Add passes to the specified pass manager to
/// implement a fast dynamic compiler for this target. Return true if this

2
lib/Target/SparcV9/SparcV9PeepholeOpts.cpp
View File

@ -12,7 +12,7 @@
//
//===----------------------------------------------------------------------===//
#include "SparcInternals.h"
#include "SparcV9Internals.h"
#include "llvm/BasicBlock.h"
#include "llvm/Pass.h"
#include "llvm/CodeGen/MachineFunction.h"

2
lib/Target/SparcV9/SparcV9PreSelection.cpp
View File

@ -15,7 +15,7 @@
//
//===----------------------------------------------------------------------===//
#include "SparcInternals.h"
#include "SparcV9Internals.h"
#include "llvm/Constants.h"
#include "llvm/DerivedTypes.h"
#include "llvm/iMemory.h"

10
lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp
View File

@ -16,8 +16,8 @@
//
//===----------------------------------------------------------------------===//
#include "SparcInternals.h"
#include "SparcRegClassInfo.h"
#include "SparcV9Internals.h"
#include "SparcV9RegClassInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineFunctionInfo.h"
#include "llvm/CodeGen/MachineCodeForInstruction.h"
@ -31,7 +31,7 @@ namespace llvm {
namespace {
struct InsertPrologEpilogCode : public MachineFunctionPass {
const char *getPassName() const { return "Sparc Prolog/Epilog Inserter"; }
const char *getPassName() const { return "SparcV9 Prolog/Epilog Inserter"; }
bool runOnMachineFunction(MachineFunction &F) {
if (!F.getInfo()->isCompiledAsLeafMethod()) {
@ -83,7 +83,7 @@ void InsertPrologEpilogCode::InsertPrologCode(MachineFunction &MF)
// SETSW -(stackSize), %g1
int uregNum = TM.getRegInfo().getUnifiedRegNum(
TM.getRegInfo().getRegClassIDOfType(Type::IntTy),
SparcIntRegClass::g1);
SparcV9IntRegClass::g1);
MachineInstr* M = BuildMI(V9::SETHI, 2).addSImm(C)
.addMReg(uregNum, MachineOperand::Def);
@ -119,7 +119,7 @@ void InsertPrologEpilogCode::InsertPrologCode(MachineFunction &MF)
bool ignore;
int firstArgReg = TM.getRegInfo().getUnifiedRegNum(
TM.getRegInfo().getRegClassIDOfType(Type::IntTy),
SparcIntRegClass::i0);
SparcV9IntRegClass::i0);
int fpReg = TM.getFrameInfo().getIncomingArgBaseRegNum();
int argSize = TM.getFrameInfo().getSizeOfEachArgOnStack();
int firstArgOffset=TM.getFrameInfo().getFirstIncomingArgOffset(MF,ignore);

56
lib/Target/SparcV9/SparcV9RegClassInfo.cpp
View File

@ -1,4 +1,4 @@
//===-- SparcRegClassInfo.cpp - Register class def'ns for Sparc -----------===//
//===-- SparcV9RegClassInfo.cpp - Register class def'ns for SparcV9 -----------===//
//
// The LLVM Compiler Infrastructure
//
@ -7,14 +7,14 @@
//
//===----------------------------------------------------------------------===//
//
// This file defines the register classes used by the Sparc target description.
// This file defines the register classes used by the SparcV9 target description.
//
//===----------------------------------------------------------------------===//
#include "llvm/Type.h"
#include "SparcRegClassInfo.h"
#include "SparcInternals.h"
#include "SparcRegInfo.h"
#include "SparcV9RegClassInfo.h"
#include "SparcV9Internals.h"
#include "SparcV9RegInfo.h"
#include "RegAlloc/RegAllocCommon.h"
#include "RegAlloc/IGNode.h"
@ -33,7 +33,7 @@ namespace llvm {
// If both above fail, spill.
//
//-----------------------------------------------------------------------------
void SparcIntRegClass::colorIGNode(IGNode * Node,
void SparcV9IntRegClass::colorIGNode(IGNode * Node,
const std::vector<bool> &IsColorUsedArr) const
{
LiveRange *LR = Node->getParentLR();
@ -69,16 +69,16 @@ void SparcIntRegClass::colorIGNode(IGNode * Node,
//if this Node is between calls
if (! LR->isCallInterference()) {
// start with volatiles (we can allocate volatiles safely)
SearchStart = SparcIntRegClass::StartOfAllRegs;
SearchStart = SparcV9IntRegClass::StartOfAllRegs;
} else {
// start with non volatiles (no non-volatiles)
SearchStart = SparcIntRegClass::StartOfNonVolatileRegs;
SearchStart = SparcV9IntRegClass::StartOfNonVolatileRegs;
}
unsigned c=0; // color
// find first unused color
for (c=SearchStart; c < SparcIntRegClass::NumOfAvailRegs; c++) {
for (c=SearchStart; c < SparcV9IntRegClass::NumOfAvailRegs; c++) {
if (!IsColorUsedArr[c]) {
ColorFound = true;
break;
@ -95,10 +95,10 @@ void SparcIntRegClass::colorIGNode(IGNode * Node,
//
else if (LR->isCallInterference()) {
// start from 0 - try to find even a volatile this time
SearchStart = SparcIntRegClass::StartOfAllRegs;
SearchStart = SparcV9IntRegClass::StartOfAllRegs;
// find first unused volatile color
for(c=SearchStart; c < SparcIntRegClass::StartOfNonVolatileRegs; c++) {
for(c=SearchStart; c < SparcV9IntRegClass::StartOfNonVolatileRegs; c++) {
if (! IsColorUsedArr[c]) {
ColorFound = true;
break;
@ -140,7 +140,7 @@ void SparcIntRegClass::colorIGNode(IGNode * Node,
// Note: The third name (%ccr) is essentially an assembly mnemonic and
// depends solely on the opcode, so the name can be chosen in EmitAssembly.
//-----------------------------------------------------------------------------
void SparcIntCCRegClass::colorIGNode(IGNode *Node,
void SparcV9IntCCRegClass::colorIGNode(IGNode *Node,
const std::vector<bool> &IsColorUsedArr) const
{
if (Node->getNumOfNeighbors() > 0)
@ -173,7 +173,7 @@ void SparcIntCCRegClass::colorIGNode(IGNode *Node,
}
void SparcFloatCCRegClass::colorIGNode(IGNode *Node,
void SparcV9FloatCCRegClass::colorIGNode(IGNode *Node,
const std::vector<bool> &IsColorUsedArr) const {
for(unsigned c = 0; c != 4; ++c)
if (!IsColorUsedArr[c]) { // find unused color
@ -201,7 +201,7 @@ void SparcFloatCCRegClass::colorIGNode(IGNode *Node,
// If a color is still not fond, mark for spilling
//
//----------------------------------------------------------------------------
void SparcFloatRegClass::colorIGNode(IGNode * Node,
void SparcV9FloatRegClass::colorIGNode(IGNode * Node,
const std::vector<bool> &IsColorUsedArr) const
{
LiveRange *LR = Node->getParentLR();
@ -211,11 +211,11 @@ void SparcFloatRegClass::colorIGNode(IGNode * Node,
//
// FIXME: This is old code that is no longer needed. Temporarily converting
// it into a big assertion just to check that the replacement logic
// (invoking SparcFloatRegClass::markColorsUsed() directly from
// (invoking SparcV9FloatRegClass::markColorsUsed() directly from
// RegClass::colorIGNode) works correctly.
//
// In fact, this entire function should be identical to
// SparcIntRegClass::colorIGNode(), and perhaps can be
// SparcV9IntRegClass::colorIGNode(), and perhaps can be
// made into a general case in CodeGen/RegAlloc/RegClass.cpp.
//
unsigned NumNeighbors = Node->getNumOfNeighbors(); // total # of neighbors
@ -242,7 +242,7 @@ void SparcFloatRegClass::colorIGNode(IGNode * Node,
// **NOTE: We don't check for call interferences in allocating suggested
// color in this class since ALL registers are volatile. If this fact
// changes, we should change the following part
//- see SparcIntRegClass::colorIGNode()
//- see SparcV9IntRegClass::colorIGNode()
//
if( LR->hasSuggestedColor() ) {
if( ! IsColorUsedArr[ LR->getSuggestedColor() ] ) {
@ -280,10 +280,10 @@ void SparcFloatRegClass::colorIGNode(IGNode * Node,
//if this Node is between calls (i.e., no call interferences )
if (! isCallInterf) {
// start with volatiles (we can allocate volatiles safely)
SearchStart = SparcFloatRegClass::StartOfAllRegs;
SearchStart = SparcV9FloatRegClass::StartOfAllRegs;
} else {
// start with non volatiles (no non-volatiles)
SearchStart = SparcFloatRegClass::StartOfNonVolatileRegs;
SearchStart = SparcV9FloatRegClass::StartOfNonVolatileRegs;
}
ColorFound = findFloatColor(LR, SearchStart, 32, IsColorUsedArr);
@ -296,8 +296,8 @@ void SparcFloatRegClass::colorIGNode(IGNode * Node,
// We are here because there is a call interference and no non-volatile
// color could be found.
// Now try to allocate even a volatile color
ColorFound = findFloatColor(LR, SparcFloatRegClass::StartOfAllRegs,
SparcFloatRegClass::StartOfNonVolatileRegs,
ColorFound = findFloatColor(LR, SparcV9FloatRegClass::StartOfAllRegs,
SparcV9FloatRegClass::StartOfNonVolatileRegs,
IsColorUsedArr);
}
@ -316,13 +316,13 @@ void SparcFloatRegClass::colorIGNode(IGNode * Node,
// for double-precision registers.
//-----------------------------------------------------------------------------
void SparcFloatRegClass::markColorsUsed(unsigned RegInClass,
void SparcV9FloatRegClass::markColorsUsed(unsigned RegInClass,
int UserRegType,
int RegTypeWanted,
std::vector<bool> &IsColorUsedArr) const
{
if (UserRegType == SparcRegInfo::FPDoubleRegType ||
RegTypeWanted == SparcRegInfo::FPDoubleRegType) {
if (UserRegType == SparcV9RegInfo::FPDoubleRegType ||
RegTypeWanted == SparcV9RegInfo::FPDoubleRegType) {
// This register is used as or is needed as a double-precision reg.
// We need to mark the [even,odd] pair corresponding to this reg.
// Get the even numbered register corresponding to this reg.
@ -346,10 +346,10 @@ void SparcFloatRegClass::markColorsUsed(unsigned RegInClass,
// for double-precision registers
// It returns -1 if no unused color is found.
//
int SparcFloatRegClass::findUnusedColor(int RegTypeWanted,
int SparcV9FloatRegClass::findUnusedColor(int RegTypeWanted,
const std::vector<bool> &IsColorUsedArr) const
{
if (RegTypeWanted == SparcRegInfo::FPDoubleRegType) {
if (RegTypeWanted == SparcV9RegInfo::FPDoubleRegType) {
unsigned NC = 2 * this->getNumOfAvailRegs();
assert(IsColorUsedArr.size() == NC && "Invalid colors-used array");
for (unsigned c = 0; c < NC; c+=2)
@ -369,7 +369,7 @@ int SparcFloatRegClass::findUnusedColor(int RegTypeWanted,
// type of the Node (i.e., float/double)
//-----------------------------------------------------------------------------
int SparcFloatRegClass::findFloatColor(const LiveRange *LR,
int SparcV9FloatRegClass::findFloatColor(const LiveRange *LR,
unsigned Start,
unsigned End,
const std::vector<bool> &IsColorUsedArr) const
@ -380,7 +380,7 @@ int SparcFloatRegClass::findFloatColor(const LiveRange *LR,
for (unsigned c=Start; c < End ; c+= 2)
if (!IsColorUsedArr[c]) {
assert(!IsColorUsedArr[c+1] &&
"Incorrect marking of used regs for Sparc FP double!");
"Incorrect marking of used regs for SparcV9 FP double!");
return c;
}
} else {

34
lib/Target/SparcV9/SparcV9RegClassInfo.h
View File

@ -1,4 +1,4 @@
//===-- SparcRegClassInfo.h - Register class def'ns for Sparc ---*- C++ -*-===//
//===-- SparcV9RegClassInfo.h - Register class def'ns for SparcV9 ---*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -7,7 +7,7 @@
//
//===----------------------------------------------------------------------===//
//
// This file defines the register classes used by the Sparc target description.
// This file defines the register classes used by the SparcV9 target description.
//
//===----------------------------------------------------------------------===//
@ -22,8 +22,8 @@ namespace llvm {
// Integer Register Class
//-----------------------------------------------------------------------------
struct SparcIntRegClass : public TargetRegClassInfo {
SparcIntRegClass(unsigned ID)
struct SparcV9IntRegClass : public TargetRegClassInfo {
SparcV9IntRegClass(unsigned ID)
: TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) { }
void colorIGNode(IGNode *Node,
@ -87,12 +87,12 @@ struct SparcIntRegClass : public TargetRegClassInfo {
// Float Register Class
//-----------------------------------------------------------------------------
class SparcFloatRegClass : public TargetRegClassInfo {
class SparcV9FloatRegClass : public TargetRegClassInfo {
int findFloatColor(const LiveRange *LR, unsigned Start,
unsigned End,
const std::vector<bool> &IsColorUsedArr) const;
public:
SparcFloatRegClass(unsigned ID)
SparcV9FloatRegClass(unsigned ID)
: TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) {}
// This method marks the registers used for a given register number.
@ -116,7 +116,7 @@ public:
void colorIGNode(IGNode *Node,
const std::vector<bool> &IsColorUsedArr) const;
// according to Sparc 64 ABI, all %fp regs are volatile
// according to SparcV9 64 ABI, all %fp regs are volatile
inline bool isRegVolatile(int Reg) const { return true; }
enum {
@ -153,14 +153,14 @@ public:
// allocated for the three names.
//-----------------------------------------------------------------------------
struct SparcIntCCRegClass : public TargetRegClassInfo {
SparcIntCCRegClass(unsigned ID)
struct SparcV9IntCCRegClass : public TargetRegClassInfo {
SparcV9IntCCRegClass(unsigned ID)
: TargetRegClassInfo(ID, 1, 3) { }
void colorIGNode(IGNode *Node,
const std::vector<bool> &IsColorUsedArr) const;
// according to Sparc 64 ABI, %ccr is volatile
// according to SparcV9 64 ABI, %ccr is volatile
//
inline bool isRegVolatile(int Reg) const { return true; }
@ -177,14 +177,14 @@ struct SparcIntCCRegClass : public TargetRegClassInfo {
// Only 4 Float CC registers are available for allocation.
//-----------------------------------------------------------------------------
struct SparcFloatCCRegClass : public TargetRegClassInfo {
SparcFloatCCRegClass(unsigned ID)
struct SparcV9FloatCCRegClass : public TargetRegClassInfo {
SparcV9FloatCCRegClass(unsigned ID)
: TargetRegClassInfo(ID, 4, 5) { }
void colorIGNode(IGNode *Node,
const std::vector<bool> &IsColorUsedArr) const;
// according to Sparc 64 ABI, all %fp CC regs are volatile
// according to SparcV9 64 ABI, all %fp CC regs are volatile
//
inline bool isRegVolatile(int Reg) const { return true; }
@ -196,17 +196,17 @@ struct SparcFloatCCRegClass : public TargetRegClassInfo {
};
//-----------------------------------------------------------------------------
// Sparc special register class. These registers are not used for allocation
// SparcV9 special register class. These registers are not used for allocation
// but are used as arguments of some instructions.
//-----------------------------------------------------------------------------
struct SparcSpecialRegClass : public TargetRegClassInfo {
SparcSpecialRegClass(unsigned ID)
struct SparcV9SpecialRegClass : public TargetRegClassInfo {
SparcV9SpecialRegClass(unsigned ID)
: TargetRegClassInfo(ID, 0, 1) { }
void colorIGNode(IGNode *Node,
const std::vector<bool> &IsColorUsedArr) const {
assert(0 && "SparcSpecialRegClass should never be used for allocation");
assert(0 && "SparcV9SpecialRegClass should never be used for allocation");
}
// all currently included special regs are volatile

170
lib/Target/SparcV9/SparcV9RegInfo.cpp
View File

@ -1,4 +1,4 @@
//===-- SparcRegInfo.cpp - Sparc Target Register Information --------------===//
//===-- SparcV9RegInfo.cpp - SparcV9 Target Register Information --------------===//
//
// The LLVM Compiler Infrastructure
//
@ -7,7 +7,7 @@
//
//===----------------------------------------------------------------------===//
//
// This file contains implementation of Sparc specific helper methods
// This file contains implementation of SparcV9 specific helper methods
// used for register allocation.
//
//===----------------------------------------------------------------------===//
@ -24,10 +24,10 @@
#include "llvm/Function.h"
#include "llvm/iTerminators.h"
#include "llvm/iOther.h"
#include "SparcInternals.h"
#include "SparcRegClassInfo.h"
#include "SparcRegInfo.h"
#include "SparcTargetMachine.h"
#include "SparcV9Internals.h"
#include "SparcV9RegClassInfo.h"
#include "SparcV9RegInfo.h"
#include "SparcV9TargetMachine.h"
namespace llvm {
@ -35,16 +35,16 @@ enum {
BadRegClass = ~0
};
SparcRegInfo::SparcRegInfo(const SparcTargetMachine &tgt)
SparcV9RegInfo::SparcV9RegInfo(const SparcV9TargetMachine &tgt)
: TargetRegInfo(tgt), NumOfIntArgRegs(6), NumOfFloatArgRegs(32)
{
MachineRegClassArr.push_back(new SparcIntRegClass(IntRegClassID));
MachineRegClassArr.push_back(new SparcFloatRegClass(FloatRegClassID));
MachineRegClassArr.push_back(new SparcIntCCRegClass(IntCCRegClassID));
MachineRegClassArr.push_back(new SparcFloatCCRegClass(FloatCCRegClassID));
MachineRegClassArr.push_back(new SparcSpecialRegClass(SpecialRegClassID));
MachineRegClassArr.push_back(new SparcV9IntRegClass(IntRegClassID));
MachineRegClassArr.push_back(new SparcV9FloatRegClass(FloatRegClassID));
MachineRegClassArr.push_back(new SparcV9IntCCRegClass(IntCCRegClassID));
MachineRegClassArr.push_back(new SparcV9FloatCCRegClass(FloatCCRegClassID));
MachineRegClassArr.push_back(new SparcV9SpecialRegClass(SpecialRegClassID));
assert(SparcFloatRegClass::StartOfNonVolatileRegs == 32 &&
assert(SparcV9FloatRegClass::StartOfNonVolatileRegs == 32 &&
"32 Float regs are used for float arg passing");
}
@ -52,31 +52,31 @@ SparcRegInfo::SparcRegInfo(const SparcTargetMachine &tgt)
// getZeroRegNum - returns the register that contains always zero.
// this is the unified register number
//
unsigned SparcRegInfo::getZeroRegNum() const {
return getUnifiedRegNum(SparcRegInfo::IntRegClassID,
SparcIntRegClass::g0);
unsigned SparcV9RegInfo::getZeroRegNum() const {
return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
SparcV9IntRegClass::g0);
}
// getCallAddressReg - returns the reg used for pushing the address when a
// method is called. This can be used for other purposes between calls
//
unsigned SparcRegInfo::getCallAddressReg() const {
return getUnifiedRegNum(SparcRegInfo::IntRegClassID,
SparcIntRegClass::o7);
unsigned SparcV9RegInfo::getCallAddressReg() const {
return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
SparcV9IntRegClass::o7);
}
// Returns the register containing the return address.
// It should be made sure that this register contains the return
// value when a return instruction is reached.
//
unsigned SparcRegInfo::getReturnAddressReg() const {
return getUnifiedRegNum(SparcRegInfo::IntRegClassID,
SparcIntRegClass::i7);
unsigned SparcV9RegInfo::getReturnAddressReg() const {
return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
SparcV9IntRegClass::i7);
}
// Register get name implementations...
// Int register names in same order as enum in class SparcIntRegClass
// Int register names in same order as enum in class SparcV9IntRegClass
static const char * const IntRegNames[] = {
"o0", "o1", "o2", "o3", "o4", "o5", "o7",
"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
@ -86,7 +86,7 @@ static const char * const IntRegNames[] = {
"o6"
};
const char * const SparcIntRegClass::getRegName(unsigned reg) const {
const char * const SparcV9IntRegClass::getRegName(unsigned reg) const {
assert(reg < NumOfAllRegs);
return IntRegNames[reg];
}
@ -101,7 +101,7 @@ static const char * const FloatRegNames[] = {
"f60", "f61", "f62", "f63"
};
const char * const SparcFloatRegClass::getRegName(unsigned reg) const {
const char * const SparcV9FloatRegClass::getRegName(unsigned reg) const {
assert (reg < NumOfAllRegs);
return FloatRegNames[reg];
}
@ -111,7 +111,7 @@ static const char * const IntCCRegNames[] = {
"xcc", "icc", "ccr"
};
const char * const SparcIntCCRegClass::getRegName(unsigned reg) const {
const char * const SparcV9IntCCRegClass::getRegName(unsigned reg) const {
assert(reg < 3);
return IntCCRegNames[reg];
}
@ -120,7 +120,7 @@ static const char * const FloatCCRegNames[] = {
"fcc0", "fcc1", "fcc2", "fcc3"
};
const char * const SparcFloatCCRegClass::getRegName(unsigned reg) const {
const char * const SparcV9FloatCCRegClass::getRegName(unsigned reg) const {
assert (reg < 5);
return FloatCCRegNames[reg];
}
@ -129,21 +129,21 @@ static const char * const SpecialRegNames[] = {
"fsr"
};
const char * const SparcSpecialRegClass::getRegName(unsigned reg) const {
const char * const SparcV9SpecialRegClass::getRegName(unsigned reg) const {
assert (reg < 1);
return SpecialRegNames[reg];
}
// Get unified reg number for frame pointer
unsigned SparcRegInfo::getFramePointer() const {
return getUnifiedRegNum(SparcRegInfo::IntRegClassID,
SparcIntRegClass::i6);
unsigned SparcV9RegInfo::getFramePointer() const {
return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
SparcV9IntRegClass::i6);
}
// Get unified reg number for stack pointer
unsigned SparcRegInfo::getStackPointer() const {
return getUnifiedRegNum(SparcRegInfo::IntRegClassID,
SparcIntRegClass::o6);
unsigned SparcV9RegInfo::getStackPointer() const {
return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
SparcV9IntRegClass::o6);
}
@ -175,14 +175,14 @@ isVarArgsCall(const MachineInstr *CallMI) {
// regClassId is set to the register class ID.
//
int
SparcRegInfo::regNumForIntArg(bool inCallee, bool isVarArgsCall,
SparcV9RegInfo::regNumForIntArg(bool inCallee, bool isVarArgsCall,
unsigned argNo, unsigned& regClassId) const
{
regClassId = IntRegClassID;
if (argNo >= NumOfIntArgRegs)
return getInvalidRegNum();
else
return argNo + (inCallee? SparcIntRegClass::i0 : SparcIntRegClass::o0);
return argNo + (inCallee? SparcV9IntRegClass::i0 : SparcV9IntRegClass::o0);
}
// Get the register number for the specified FP argument #argNo,
@ -194,7 +194,7 @@ SparcRegInfo::regNumForIntArg(bool inCallee, bool isVarArgsCall,
// regClassId is set to the register class ID.
//
int
SparcRegInfo::regNumForFPArg(unsigned regType,
SparcV9RegInfo::regNumForFPArg(unsigned regType,
bool inCallee, bool isVarArgsCall,
unsigned argNo, unsigned& regClassId) const
{
@ -205,10 +205,10 @@ SparcRegInfo::regNumForFPArg(unsigned regType,
regClassId = FloatRegClassID;
if (regType == FPSingleRegType)
return (argNo*2+1 >= NumOfFloatArgRegs)?
getInvalidRegNum() : SparcFloatRegClass::f0 + (argNo * 2 + 1);
getInvalidRegNum() : SparcV9FloatRegClass::f0 + (argNo * 2 + 1);
else if (regType == FPDoubleRegType)
return (argNo*2 >= NumOfFloatArgRegs)?
getInvalidRegNum() : SparcFloatRegClass::f0 + (argNo * 2);
getInvalidRegNum() : SparcV9FloatRegClass::f0 + (argNo * 2);
else
assert(0 && "Illegal FP register type");
return 0;
@ -220,10 +220,10 @@ SparcRegInfo::regNumForFPArg(unsigned regType,
// Finds the return address of a call sparc specific call instruction
//---------------------------------------------------------------------------
// The following 4 methods are used to find the RegType (SparcInternals.h)
// The following 4 methods are used to find the RegType (SparcV9Internals.h)
// of a LiveRange, a Value, and for a given register unified reg number.
//
int SparcRegInfo::getRegTypeForClassAndType(unsigned regClassID,
int SparcV9RegInfo::getRegTypeForClassAndType(unsigned regClassID,
const Type* type) const
{
switch (regClassID) {
@ -239,17 +239,17 @@ int SparcRegInfo::getRegTypeForClassAndType(unsigned regClassID,
}
}
int SparcRegInfo::getRegTypeForDataType(const Type* type) const
int SparcV9RegInfo::getRegTypeForDataType(const Type* type) const
{
return getRegTypeForClassAndType(getRegClassIDOfType(type), type);
}
int SparcRegInfo::getRegTypeForLR(const LiveRange *LR) const
int SparcV9RegInfo::getRegTypeForLR(const LiveRange *LR) const
{
return getRegTypeForClassAndType(LR->getRegClassID(), LR->getType());
}
int SparcRegInfo::getRegType(int unifiedRegNum) const
int SparcV9RegInfo::getRegType(int unifiedRegNum) const
{
if (unifiedRegNum < 32)
return IntRegType;
@ -269,7 +269,7 @@ int SparcRegInfo::getRegType(int unifiedRegNum) const
// To find the register class used for a specified Type
//
unsigned SparcRegInfo::getRegClassIDOfType(const Type *type,
unsigned SparcV9RegInfo::getRegClassIDOfType(const Type *type,
bool isCCReg) const {
Type::PrimitiveID ty = type->getPrimitiveID();
unsigned res;
@ -292,7 +292,7 @@ unsigned SparcRegInfo::getRegClassIDOfType(const Type *type,
return res;
}
unsigned SparcRegInfo::getRegClassIDOfRegType(int regType) const {
unsigned SparcV9RegInfo::getRegClassIDOfRegType(int regType) const {
switch(regType) {
case IntRegType: return IntRegClassID;
case FPSingleRegType:
@ -309,14 +309,14 @@ unsigned SparcRegInfo::getRegClassIDOfRegType(int regType) const {
// Suggests a register for the ret address in the RET machine instruction.
// We always suggest %i7 by convention.
//---------------------------------------------------------------------------
void SparcRegInfo::suggestReg4RetAddr(MachineInstr *RetMI,
void SparcV9RegInfo::suggestReg4RetAddr(MachineInstr *RetMI,
LiveRangeInfo& LRI) const {
assert(target.getInstrInfo().isReturn(RetMI->getOpcode()));
// return address is always mapped to i7 so set it immediately
RetMI->SetRegForOperand(0, getUnifiedRegNum(IntRegClassID,
SparcIntRegClass::i7));
SparcV9IntRegClass::i7));
// Possible Optimization:
// Instead of setting the color, we can suggest one. In that case,
@ -329,16 +329,16 @@ void SparcRegInfo::suggestReg4RetAddr(MachineInstr *RetMI,
// assert( RetAddrVal && "LR for ret address must be created at start");
// LiveRange * RetAddrLR = LRI.getLiveRangeForValue( RetAddrVal);
// RetAddrLR->setSuggestedColor(getUnifiedRegNum( IntRegClassID,
// SparcIntRegOrdr::i7) );
// SparcV9IntRegOrdr::i7) );
}
//---------------------------------------------------------------------------
// Suggests a register for the ret address in the JMPL/CALL machine instr.
// Sparc ABI dictates that %o7 be used for this purpose.
// SparcV9 ABI dictates that %o7 be used for this purpose.
//---------------------------------------------------------------------------
void
SparcRegInfo::suggestReg4CallAddr(MachineInstr * CallMI,
SparcV9RegInfo::suggestReg4CallAddr(MachineInstr * CallMI,
LiveRangeInfo& LRI) const
{
CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
@ -350,19 +350,19 @@ SparcRegInfo::suggestReg4CallAddr(MachineInstr * CallMI,
assert(RetAddrLR && "INTERNAL ERROR: No LR for return address of call!");
unsigned RegClassID = RetAddrLR->getRegClassID();
RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID, SparcIntRegClass::o7));
RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID, SparcV9IntRegClass::o7));
}
//---------------------------------------------------------------------------
// This method will suggest colors to incoming args to a method.
// According to the Sparc ABI, the first 6 incoming args are in
// According to the SparcV9 ABI, the first 6 incoming args are in
// %i0 - %i5 (if they are integer) OR in %f0 - %f31 (if they are float).
// If the arg is passed on stack due to the lack of regs, NOTHING will be
// done - it will be colored (or spilled) as a normal live range.
//---------------------------------------------------------------------------
void SparcRegInfo::suggestRegs4MethodArgs(const Function *Meth,
void SparcV9RegInfo::suggestRegs4MethodArgs(const Function *Meth,
LiveRangeInfo& LRI) const
{
// Check if this is a varArgs function. needed for choosing regs.
@ -395,7 +395,7 @@ void SparcRegInfo::suggestRegs4MethodArgs(const Function *Meth,
// the correct hardware registers if they did not receive the correct
// (suggested) color through graph coloring.
//---------------------------------------------------------------------------
void SparcRegInfo::colorMethodArgs(const Function *Meth,
void SparcV9RegInfo::colorMethodArgs(const Function *Meth,
LiveRangeInfo &LRI,
std::vector<MachineInstr*>& InstrnsBefore,
std::vector<MachineInstr*>& InstrnsAfter) const {
@ -568,7 +568,7 @@ void SparcRegInfo::colorMethodArgs(const Function *Meth,
// This method is called before graph coloring to suggest colors to the
// outgoing call args and the return value of the call.
//---------------------------------------------------------------------------
void SparcRegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
void SparcV9RegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
LiveRangeInfo& LRI) const {
assert ( (target.getInstrInfo()).isCall(CallMI->getOpcode()) );
@ -588,9 +588,9 @@ void SparcRegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
// now suggest a register depending on the register class of ret arg
if( RegClassID == IntRegClassID )
RetValLR->setSuggestedColor(SparcIntRegClass::o0);
RetValLR->setSuggestedColor(SparcV9IntRegClass::o0);
else if (RegClassID == FloatRegClassID )
RetValLR->setSuggestedColor(SparcFloatRegClass::f0 );
RetValLR->setSuggestedColor(SparcV9FloatRegClass::f0 );
else assert( 0 && "Unknown reg class for return value of call\n");
}
@ -636,7 +636,7 @@ void SparcRegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
// this method is called for an LLVM return instruction to identify which
// values will be returned from this method and to suggest colors.
//---------------------------------------------------------------------------
void SparcRegInfo::suggestReg4RetValue(MachineInstr *RetMI,
void SparcV9RegInfo::suggestReg4RetValue(MachineInstr *RetMI,
LiveRangeInfo& LRI) const {
assert( (target.getInstrInfo()).isReturn( RetMI->getOpcode() ) );
@ -650,8 +650,8 @@ void SparcRegInfo::suggestReg4RetValue(MachineInstr *RetMI,
if (const Value *RetVal = retI->getReturnValue())
if (LiveRange *const LR = LRI.getLiveRangeForValue(RetVal))
LR->setSuggestedColor(LR->getRegClassID() == IntRegClassID
? (unsigned) SparcIntRegClass::i0
: (unsigned) SparcFloatRegClass::f0);
? (unsigned) SparcV9IntRegClass::i0
: (unsigned) SparcV9FloatRegClass::f0);
}
//---------------------------------------------------------------------------
@ -664,7 +664,7 @@ void SparcRegInfo::suggestReg4RetValue(MachineInstr *RetMI,
//---------------------------------------------------------------------------
bool
SparcRegInfo::regTypeNeedsScratchReg(int RegType,
SparcV9RegInfo::regTypeNeedsScratchReg(int RegType,
int& scratchRegType) const
{
if (RegType == IntCCRegType)
@ -681,7 +681,7 @@ SparcRegInfo::regTypeNeedsScratchReg(int RegType,
//---------------------------------------------------------------------------
void
SparcRegInfo::cpReg2RegMI(std::vector<MachineInstr*>& mvec,
SparcV9RegInfo::cpReg2RegMI(std::vector<MachineInstr*>& mvec,
unsigned SrcReg,
unsigned DestReg,
int RegType) const {
@ -697,8 +697,8 @@ SparcRegInfo::cpReg2RegMI(std::vector<MachineInstr*>& mvec,
if (getRegType(DestReg) == IntRegType) {
// copy intCC reg to int reg
MI = (BuildMI(V9::RDCCR, 2)
.addMReg(getUnifiedRegNum(SparcRegInfo::IntCCRegClassID,
SparcIntCCRegClass::ccr))
.addMReg(getUnifiedRegNum(SparcV9RegInfo::IntCCRegClassID,
SparcV9IntCCRegClass::ccr))
.addMReg(DestReg,MachineOperand::Def));
} else {
// copy int reg to intCC reg
@ -706,9 +706,9 @@ SparcRegInfo::cpReg2RegMI(std::vector<MachineInstr*>& mvec,
&& "Can only copy CC reg to/from integer reg");
MI = (BuildMI(V9::WRCCRr, 3)
.addMReg(SrcReg)
.addMReg(SparcIntRegClass::g0)
.addMReg(getUnifiedRegNum(SparcRegInfo::IntCCRegClassID,
SparcIntCCRegClass::ccr),
.addMReg(SparcV9IntRegClass::g0)
.addMReg(getUnifiedRegNum(SparcV9RegInfo::IntCCRegClassID,
SparcV9IntCCRegClass::ccr),
MachineOperand::Def));
}
break;
@ -748,7 +748,7 @@ SparcRegInfo::cpReg2RegMI(std::vector<MachineInstr*>& mvec,
void
SparcRegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
SparcV9RegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
unsigned SrcReg,
unsigned PtrReg,
int Offset, int RegType,
@ -768,8 +768,8 @@ SparcRegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
#else
// Default to using register g4 for holding large offsets
OffReg = getUnifiedRegNum(SparcRegInfo::IntRegClassID,
SparcIntRegClass::g4);
OffReg = getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
SparcV9IntRegClass::g4);
#endif
assert(OffReg >= 0 && "FIXME: cpReg2MemMI cannot find an unused reg.");
mvec.push_back(BuildMI(V9::SETSW, 2).addZImm(Offset).addReg(OffReg));
@ -801,8 +801,8 @@ SparcRegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
assert(scratchReg >= 0 && "Need scratch reg to store %ccr to memory");
assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg");
MI = (BuildMI(V9::RDCCR, 2)
.addMReg(getUnifiedRegNum(SparcRegInfo::IntCCRegClassID,
SparcIntCCRegClass::ccr))
.addMReg(getUnifiedRegNum(SparcV9RegInfo::IntCCRegClassID,
SparcV9IntCCRegClass::ccr))
.addMReg(scratchReg, MachineOperand::Def));
mvec.push_back(MI);
@ -810,8 +810,8 @@ SparcRegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
return;
case FloatCCRegType: {
unsigned fsrReg = getUnifiedRegNum(SparcRegInfo::SpecialRegClassID,
SparcSpecialRegClass::fsr);
unsigned fsrReg = getUnifiedRegNum(SparcV9RegInfo::SpecialRegClassID,
SparcV9SpecialRegClass::fsr);
if (target.getInstrInfo().constantFitsInImmedField(V9::STXFSRi, Offset))
MI=BuildMI(V9::STXFSRi,3).addMReg(fsrReg).addMReg(PtrReg).addSImm(Offset);
else
@ -832,7 +832,7 @@ SparcRegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
void
SparcRegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
SparcV9RegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
unsigned PtrReg,
int Offset,
unsigned DestReg,
@ -853,8 +853,8 @@ SparcRegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
#else
// Default to using register g4 for holding large offsets
OffReg = getUnifiedRegNum(SparcRegInfo::IntRegClassID,
SparcIntRegClass::g4);
OffReg = getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
SparcV9IntRegClass::g4);
#endif
assert(OffReg >= 0 && "FIXME: cpReg2MemMI cannot find an unused reg.");
mvec.push_back(BuildMI(V9::SETSW, 2).addZImm(Offset).addReg(OffReg));
@ -894,14 +894,14 @@ SparcRegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
cpMem2RegMI(mvec, PtrReg, Offset, scratchReg, IntRegType);
MI = (BuildMI(V9::WRCCRr, 3)
.addMReg(scratchReg)
.addMReg(SparcIntRegClass::g0)
.addMReg(getUnifiedRegNum(SparcRegInfo::IntCCRegClassID,
SparcIntCCRegClass::ccr), MachineOperand::Def));
.addMReg(SparcV9IntRegClass::g0)
.addMReg(getUnifiedRegNum(SparcV9RegInfo::IntCCRegClassID,
SparcV9IntCCRegClass::ccr), MachineOperand::Def));
break;
case FloatCCRegType: {
unsigned fsrRegNum = getUnifiedRegNum(SparcRegInfo::SpecialRegClassID,
SparcSpecialRegClass::fsr);
unsigned fsrRegNum = getUnifiedRegNum(SparcV9RegInfo::SpecialRegClassID,
SparcV9SpecialRegClass::fsr);
if (target.getInstrInfo().constantFitsInImmedField(V9::LDXFSRi, Offset))
MI = BuildMI(V9::LDXFSRi, 3).addMReg(PtrReg).addSImm(Offset)
.addMReg(fsrRegNum, MachineOperand::UseAndDef);
@ -924,7 +924,7 @@ SparcRegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
void
SparcRegInfo::cpValue2Value(Value *Src, Value *Dest,
SparcV9RegInfo::cpValue2Value(Value *Src, Value *Dest,
std::vector<MachineInstr*>& mvec) const {
int RegType = getRegTypeForDataType(Src->getType());
MachineInstr * MI = NULL;
@ -953,7 +953,7 @@ SparcRegInfo::cpValue2Value(Value *Src, Value *Dest,
// Print the register assigned to a LR
//---------------------------------------------------------------------------
void SparcRegInfo::printReg(const LiveRange *LR) const {
void SparcV9RegInfo::printReg(const LiveRange *LR) const {
unsigned RegClassID = LR->getRegClassID();
std::cerr << " Node ";

20
lib/Target/SparcV9/SparcV9RegInfo.h
View File

@ -1,4 +1,4 @@
//===-- SparcRegInfo.h - Define TargetRegInfo for Sparc ---------*- C++ -*-===//
//===-- SparcV9RegInfo.h - Define TargetRegInfo for SparcV9 ---------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -7,7 +7,7 @@
//
//===----------------------------------------------------------------------===//
//
// This class implements the virtual class TargetRegInfo for Sparc.
// This class implements the virtual class TargetRegInfo for SparcV9.
//
//----------------------------------------------------------------------------
@ -18,9 +18,9 @@
namespace llvm {
class SparcTargetMachine;
class SparcV9TargetMachine;
class SparcRegInfo : public TargetRegInfo {
class SparcV9RegInfo : public TargetRegInfo {
private:
@ -34,7 +34,7 @@ private:
// The following methods are used to color special live ranges (e.g.
// function args and return values etc.) with specific hardware registers
// as required. See SparcRegInfo.cpp for the implementation.
// as required. See SparcV9RegInfo.cpp for the implementation.
//
void suggestReg4RetAddr(MachineInstr *RetMI,
LiveRangeInfo &LRI) const;
@ -45,7 +45,7 @@ private:
int getRegTypeForClassAndType(unsigned regClassID, const Type* type) const;
public:
// Type of registers available in Sparc. There can be several reg types
// Type of registers available in SparcV9. There can be several reg types
// in the same class. For instace, the float reg class has Single/Double
// types
//
@ -58,7 +58,7 @@ public:
SpecialRegType
};
// The actual register classes in the Sparc
// The actual register classes in the SparcV9
//
// **** WARNING: If this enum order is changed, also modify
// getRegisterClassOfValue method below since it assumes this particular
@ -72,7 +72,7 @@ public:
SpecialRegClassID // Special (unallocated) registers
};
SparcRegInfo(const SparcTargetMachine &tgt);
SparcV9RegInfo(const SparcV9TargetMachine &tgt);
// To find the register class used for a specified Type
//
@ -115,7 +115,7 @@ public:
// The following methods are used to color special live ranges (e.g.
// function args and return values etc.) with specific hardware registers
// as required. See SparcRegInfo.cpp for the implementation for Sparc.
// as required. See SparcV9RegInfo.cpp for the implementation for SparcV9.
//
void suggestRegs4MethodArgs(const Function *Meth,
LiveRangeInfo& LRI) const;
@ -135,7 +135,7 @@ public:
void printReg(const LiveRange *LR) const;
// returns the # of bytes of stack space allocated for each register
// type. For Sparc, currently we allocate 8 bytes on stack for all
// type. For SparcV9, currently we allocate 8 bytes on stack for all
// register types. We can optimize this later if necessary to save stack
// space (However, should make sure that stack alignment is correct)
//

36
lib/Target/SparcV9/SparcV9SchedInfo.cpp
View File

@ -1,4 +1,4 @@
//===-- UltraSparcSchedInfo.cpp -------------------------------------------===//
//===-- UltraSparcV9SchedInfo.cpp -------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@ -7,11 +7,11 @@
//
//===----------------------------------------------------------------------===//
//
// Describe the scheduling characteristics of the UltraSparc
// Describe the scheduling characteristics of the UltraSparcV9
//
//===----------------------------------------------------------------------===//
#include "SparcInternals.h"
#include "SparcV9Internals.h"
using namespace llvm;
@ -129,7 +129,7 @@ static const CPUResource FCMPDelayCycle("FCMP delay cycle", 1);
//---------------------------------------------------------------------------
// const InstrClassRUsage SparcRUsageDesc[]
// const InstrClassRUsage SparcV9RUsageDesc[]
//
// Purpose:
// Resource usage information for instruction in each scheduling class.
@ -396,7 +396,7 @@ static const InstrClassRUsage SingleClassRUsage = {
};
static const InstrClassRUsage SparcRUsageDesc[] = {
static const InstrClassRUsage SparcV9RUsageDesc[] = {
NoneClassRUsage,
IEUNClassRUsage,
IEU0ClassRUsage,
@ -412,14 +412,14 @@ static const InstrClassRUsage SparcRUsageDesc[] = {
//---------------------------------------------------------------------------
// const InstrIssueDelta SparcInstrIssueDeltas[]
// const InstrIssueDelta SparcV9InstrIssueDeltas[]
//
// Purpose:
// Changes to issue restrictions information in InstrClassRUsage for
// instructions that differ from other instructions in their class.
//---------------------------------------------------------------------------
static const InstrIssueDelta SparcInstrIssueDeltas[] = {
static const InstrIssueDelta SparcV9InstrIssueDeltas[] = {
// opCode, isSingleIssue, breaksGroup, numBubbles
@ -504,14 +504,14 @@ static const InstrIssueDelta SparcInstrIssueDeltas[] = {
//---------------------------------------------------------------------------
// const InstrRUsageDelta SparcInstrUsageDeltas[]
// const InstrRUsageDelta SparcV9InstrUsageDeltas[]
//
// Purpose:
// Changes to resource usage information in InstrClassRUsage for
// instructions that differ from other instructions in their class.
//---------------------------------------------------------------------------
static const InstrRUsageDelta SparcInstrUsageDeltas[] = {
static const InstrRUsageDelta SparcV9InstrUsageDeltas[] = {
// MachineOpCode, Resource, Start cycle, Num cycles
@ -601,7 +601,7 @@ static const InstrRUsageDelta SparcInstrUsageDeltas[] = {
#ifdef EXPLICIT_BUBBLES_NEEDED
//
// MULScc inserts one bubble.
// This means it breaks the current group (captured in UltraSparcSchedInfo)
// This means it breaks the current group (captured in UltraSparcV9SchedInfo)
// *and occupies all issue slots for the next cycle
//
//{ V9::MULScc, AllIssueSlots.rid, 2, 2-1 },
@ -728,7 +728,7 @@ static const InstrRUsageDelta SparcInstrUsageDeltas[] = {
//---------------------------------------------------------------------------
// class SparcSchedInfo
// class SparcV9SchedInfo
//
// Purpose:
// Scheduling information for the UltraSPARC.
@ -737,14 +737,14 @@ static const InstrRUsageDelta SparcInstrUsageDeltas[] = {
//---------------------------------------------------------------------------
/*ctor*/
SparcSchedInfo::SparcSchedInfo(const TargetMachine& tgt)
SparcV9SchedInfo::SparcV9SchedInfo(const TargetMachine& tgt)
: TargetSchedInfo(tgt,
(unsigned int) SPARC_NUM_SCHED_CLASSES,
SparcRUsageDesc,
SparcInstrUsageDeltas,
SparcInstrIssueDeltas,
sizeof(SparcInstrUsageDeltas)/sizeof(InstrRUsageDelta),
sizeof(SparcInstrIssueDeltas)/sizeof(InstrIssueDelta))
SparcV9RUsageDesc,
SparcV9InstrUsageDeltas,
SparcV9InstrIssueDeltas,
sizeof(SparcV9InstrUsageDeltas)/sizeof(InstrRUsageDelta),
sizeof(SparcV9InstrIssueDeltas)/sizeof(InstrIssueDelta))
{
maxNumIssueTotal = 4;
longestIssueConflict = 0; // computed from issuesGaps[]
@ -764,7 +764,7 @@ SparcSchedInfo::SparcSchedInfo(const TargetMachine& tgt)
}
void
SparcSchedInfo::initializeResources()
SparcV9SchedInfo::initializeResources()
{
// Compute TargetSchedInfo::instrRUsages and TargetSchedInfo::issueGaps
TargetSchedInfo::initializeResources();

32
lib/Target/SparcV9/SparcV9TargetMachine.cpp
View File

@ -1,4 +1,4 @@
//===-- Sparc.cpp - General implementation file for the Sparc Target ------===//
//===-- SparcV9.cpp - General implementation file for the SparcV9 Target ------===//
//
// The LLVM Compiler Infrastructure
//
@ -26,21 +26,21 @@
#include "llvm/Target/TargetMachineImpls.h"
#include "llvm/Transforms/Scalar.h"
#include "MappingInfo.h"
#include "SparcInternals.h"
#include "SparcTargetMachine.h"
#include "SparcV9Internals.h"
#include "SparcV9TargetMachine.h"
#include "Support/CommandLine.h"
using namespace llvm;
static const unsigned ImplicitRegUseList[] = { 0 }; /* not used yet */
// Build the MachineInstruction Description Array...
const TargetInstrDescriptor llvm::SparcMachineInstrDesc[] = {
const TargetInstrDescriptor llvm::SparcV9MachineInstrDesc[] = {
#define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
{ OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS, 0, \
ImplicitRegUseList, ImplicitRegUseList },
#include "SparcInstr.def"
#include "SparcV9Instr.def"
};
//---------------------------------------------------------------------------
@ -106,13 +106,13 @@ namespace {
}
}
FunctionPass *llvm::createSparcMachineCodeDestructionPass() {
FunctionPass *llvm::createSparcV9MachineCodeDestructionPass() {
return new DestroyMachineFunction();
}
SparcTargetMachine::SparcTargetMachine(IntrinsicLowering *il)
: TargetMachine("UltraSparc-Native", il, false),
SparcV9TargetMachine::SparcV9TargetMachine(IntrinsicLowering *il)
: TargetMachine("UltraSparcV9-Native", il, false),
schedInfo(*this),
regInfo(*this),
frameInfo(*this),
@ -124,7 +124,7 @@ SparcTargetMachine::SparcTargetMachine(IntrinsicLowering *il)
/// process for the ultra sparc.
///
bool
SparcTargetMachine::addPassesToEmitAssembly(PassManager &PM, std::ostream &Out)
SparcV9TargetMachine::addPassesToEmitAssembly(PassManager &PM, std::ostream &Out)
{
// The following 3 passes used to be inserted specially by llc.
// Replace malloc and free instructions with library calls.
@ -177,7 +177,7 @@ SparcTargetMachine::addPassesToEmitAssembly(PassManager &PM, std::ostream &Out)
// allowing machine code representations for functions to be free'd after the
// function has been emitted.
PM.add(createAsmPrinterPass(Out, *this));
PM.add(createSparcMachineCodeDestructionPass()); // Free mem no longer needed
PM.add(createSparcV9MachineCodeDestructionPass()); // Free mem no longer needed
// Emit bytecode to the assembly file into its special section next
if (EmitMappingInfo)
@ -187,9 +187,9 @@ SparcTargetMachine::addPassesToEmitAssembly(PassManager &PM, std::ostream &Out)
}
/// addPassesToJITCompile - This method controls the JIT method of code
/// generation for the UltraSparc.
/// generation for the UltraSparcV9.
///
void SparcJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
void SparcV9JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
const TargetData &TD = TM.getTargetData();
PM.add(new TargetData("lli", TD.isLittleEndian(), TD.getPointerSize(),
@ -229,10 +229,10 @@ void SparcJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
PM.add(createPeepholeOptsPass(TM));
}
/// allocateSparcTargetMachine - Allocate and return a subclass of TargetMachine
/// that implements the Sparc backend. (the llvm/CodeGen/Sparc.h interface)
/// allocateSparcV9TargetMachine - Allocate and return a subclass of TargetMachine
/// that implements the SparcV9 backend. (the llvm/CodeGen/SparcV9.h interface)
///
TargetMachine *llvm::allocateSparcTargetMachine(const Module &M,
TargetMachine *llvm::allocateSparcV9TargetMachine(const Module &M,
IntrinsicLowering *IL) {
return new SparcTargetMachine(IL);
return new SparcV9TargetMachine(IL);
}

28
lib/Target/SparcV9/SparcV9TargetMachine.h
View File

@ -1,4 +1,4 @@
//===-- SparcTargetMachine.h - Define TargetMachine for Sparc ---*- C++ -*-===//
//===-- SparcV9TargetMachine.h - Define TargetMachine for SparcV9 ---*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -16,24 +16,24 @@
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "SparcInstrInfo.h"
#include "SparcInternals.h"
#include "SparcRegInfo.h"
#include "SparcFrameInfo.h"
#include "SparcJITInfo.h"
#include "SparcV9InstrInfo.h"
#include "SparcV9Internals.h"
#include "SparcV9RegInfo.h"
#include "SparcV9FrameInfo.h"
#include "SparcV9JITInfo.h"
namespace llvm {
class PassManager;
class SparcTargetMachine : public TargetMachine {
SparcInstrInfo instrInfo;
SparcSchedInfo schedInfo;
SparcRegInfo regInfo;
SparcFrameInfo frameInfo;
SparcCacheInfo cacheInfo;
SparcJITInfo jitInfo;
class SparcV9TargetMachine : public TargetMachine {
SparcV9InstrInfo instrInfo;
SparcV9SchedInfo schedInfo;
SparcV9RegInfo regInfo;
SparcV9FrameInfo frameInfo;
SparcV9CacheInfo cacheInfo;
SparcV9JITInfo jitInfo;
public:
SparcTargetMachine(IntrinsicLowering *IL);
SparcV9TargetMachine(IntrinsicLowering *IL);
virtual const TargetInstrInfo &getInstrInfo() const { return instrInfo; }
virtual const TargetSchedInfo &getSchedInfo() const { return schedInfo; }

8
lib/Target/SparcV9/SparcV9_F2.td
View File

@ -1,4 +1,4 @@
//===- SparcV9_F2.td - Format 2 instructions: Sparc V9 Target -------------===//
//===- SparcV9_F2.td - Format 2 instructions: SparcV9 V9 Target -------------===//
//
// The LLVM Compiler Infrastructure
//
@ -32,7 +32,7 @@ class F2_br : F2 { // Format 2 Branch instruction
class F2_2<bits<4> cond, string name> : F2_br { // Format 2.2 instructions
bits<22> disp;
bit annul = 0; // currently unused by Sparc backend
bit annul = 0; // currently unused by SparcV9 backend
let Name = name;
let Inst{29} = annul;
@ -44,7 +44,7 @@ class F2_3<bits<4> cond, string name> : F2_br { // Format 2.3 instructions
bits<2> cc;
bits<19> disp;
bit predict = 1;
bit annul = 0; // currently unused by Sparc backend
bit annul = 0; // currently unused by SparcV9 backend
let Name = name;
let Inst{29} = annul;
@ -58,7 +58,7 @@ class F2_4<bits<3> rcond, string name> : F2_br { // Format 2.4 instructions
bits<5> rs1;
bits<16> disp;
bit predict = 1;
bit annul = 0; // currently unused by Sparc backend
bit annul = 0; // currently unused by SparcV9 backend
let Name = name;
let Inst{29} = annul;

2
lib/Target/SparcV9/SparcV9_F3.td
View File

@ -1,4 +1,4 @@
//===- SparcV9_F3.td - Format 3 Instructions: Sparc V9 Target -------------===//
//===- SparcV9_F3.td - Format 3 Instructions: SparcV9 V9 Target -------------===//
//
// The LLVM Compiler Infrastructure
//

2
lib/Target/SparcV9/SparcV9_F4.td
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@ -1,4 +1,4 @@
//===- SparcV9_F4.td - Format 4 instructions: Sparc V9 Target -------------===//
//===- SparcV9_F4.td - Format 4 instructions: SparcV9 V9 Target -------------===//
//
// The LLVM Compiler Infrastructure
//

4
lib/Target/SparcV9/SparcV9_Reg.td
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//===- SparcV9_Reg.td - Sparc V9 Register definitions ---------------------===//
//===- SparcV9_Reg.td - SparcV9 V9 Register definitions ---------------------===//
//
// The LLVM Compiler Infrastructure
//
@ -8,7 +8,7 @@
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Declarations that describe the Sparc register file
// Declarations that describe the SparcV9 register file
//===----------------------------------------------------------------------===//
// Ri - One of the 32 64 bit integer registers