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Re-enable elimination of unnecessary SUBREG_TO_REG instructions in
LowerSubregs, and fix an x86-64 isel bug that this exposed. SUBREG_TO_REG for x86-64 implicit zero extension is only safe for isel to generate when the source is known to always have zeros in the high 32 bits. The EXTRACT_SUBREG instruction does not clear the high 32 bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54444 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -108,15 +108,20 @@ bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
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DOUT << "subreg: CONVERTING: " << *MI;
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// Insert sub-register copy
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const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
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const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
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TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
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if (DstSubReg == InsReg) {
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// No need to insert an identify copy instruction.
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DOUT << "subreg: eliminated!";
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} else {
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// Insert sub-register copy
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const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
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const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
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TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
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#ifndef NDEBUG
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MachineBasicBlock::iterator dMI = MI;
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DOUT << "subreg: " << *(--dMI);
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#endif
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}
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DOUT << "\n";
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MBB->erase(MI);
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