6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2026-04-21 23:17:16 +00:00
Code Issues Projects Releases Wiki Activity

Use SuperRegClassIterator for findRepresentativeClass().

Browse Source 
The masks returned by SuperRegClassIterator are computed automatically
by TableGen. This is better than depending on the manually specified
SuperRegClasses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156147 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2012-05-04 02:19:22 +00:00
parent ed277f3eeb
commit e3ee49fb27
2 changed files with 16 additions and 31 deletions
Download Patch File Download Diff File Expand all files Collapse all files
include/llvm/Target/TargetLowering.h
-4
View File
@@ -2032,10 +2032,6 @@ private:
/// isLegalRC - Return true if the value types that can be represented by the
/// specified register class are all legal.
bool isLegalRC(const TargetRegisterClass *RC) const;
/// hasLegalSuperRegRegClasses - Return true if the specified register class
/// has one or more super-reg register classes that are legal.
bool hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const;
};
/// GetReturnInfo - Given an LLVM IR type and return type attributes,