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Move the AddLiveIn function definition closer to its uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69382 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -478,17 +478,6 @@ static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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State);
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}
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/// AddLiveIn - This helper function adds the specified physical register to the
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/// MachineFunction as a live in value. It also creates a corresponding virtual
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/// register for it.
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static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
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const TargetRegisterClass *RC) {
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assert(RC->contains(PReg) && "Not the correct regclass!");
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unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
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MF.getRegInfo().addLiveIn(PReg, VReg);
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return VReg;
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}
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/// LowerCallResult - Lower the result values of an ISD::CALL into the
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/// appropriate copies out of appropriate physical registers. This assumes that
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/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
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@ -1064,6 +1053,17 @@ static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
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return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
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}
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/// AddLiveIn - This helper function adds the specified physical register to the
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/// MachineFunction as a live-in value. It also creates a corresponding virtual
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/// register for it.
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static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
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const TargetRegisterClass *RC) {
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assert(RC->contains(PReg) && "Not the correct regclass!");
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unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
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MF.getRegInfo().addLiveIn(PReg, VReg);
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return VReg;
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}
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SDValue
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ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
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MachineFunction &MF = DAG.getMachineFunction();
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