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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234506 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2015-04-09 17:10:57 +00:00
parent 154e053687
commit e4053cd377
4 changed files with 22 additions and 24 deletions
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13
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
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@ -41,9 +41,8 @@ extern Target TheARMBETarget, TheThumbBETarget;
namespace ARM_MC {
std::string ParseARMTriple(StringRef TT, StringRef CPU);
/// createARMMCSubtargetInfo - Create a ARM MCSubtargetInfo instance.
/// This is exposed so Asm parser, etc. do not need to go through
/// TargetRegistry.
/// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc.
/// do not need to go through TargetRegistry.
MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS);
}
@ -86,21 +85,21 @@ MCStreamer *createARMWinCOFFStreamer(MCContext &Context, MCAsmBackend &MAB,
raw_ostream &OS, MCCodeEmitter *Emitter,
bool RelaxAll);
/// createARMELFObjectWriter - Construct an ELF Mach-O object writer.
/// Construct an ELF Mach-O object writer.
MCObjectWriter *createARMELFObjectWriter(raw_ostream &OS,
uint8_t OSABI,
bool IsLittleEndian);
/// createARMMachObjectWriter - Construct an ARM Mach-O object writer.
/// Construct an ARM Mach-O object writer.
MCObjectWriter *createARMMachObjectWriter(raw_ostream &OS,
bool Is64Bit,
uint32_t CPUType,
uint32_t CPUSubtype);
/// createARMWinCOFFObjectWriter - Construct an ARM PE/COFF object writer.
/// Construct an ARM PE/COFF object writer.
MCObjectWriter *createARMWinCOFFObjectWriter(raw_ostream &OS, bool Is64Bit);
/// createARMMachORelocationInfo - Construct ARM Mach-O relocation info.
/// Construct ARM Mach-O relocation info.
MCRelocationInfo *createARMMachORelocationInfo(MCContext &Ctx);
} // End llvm namespace

2
lib/Target/Hexagon/MCTargetDesc/HexagonELFObjectWriter.cpp
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@ -60,4 +60,4 @@ MCObjectWriter *llvm::createHexagonELFObjectWriter(raw_ostream &OS,
StringRef CPU) {
MCELFObjectTargetWriter *MOTW = new HexagonELFObjectWriter(OSABI, CPU);
return createELFObjectWriter(MOTW, OS, /*IsLittleEndian*/ true);
}
}

12
lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
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@ -43,20 +43,20 @@ MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII,
MCAsmBackend *createPPCAsmBackend(const Target &T, const MCRegisterInfo &MRI,
StringRef TT, StringRef CPU);
/// createPPCELFObjectWriter - Construct an PPC ELF object writer.
/// Construct an PPC ELF object writer.
MCObjectWriter *createPPCELFObjectWriter(raw_ostream &OS,
bool Is64Bit,
bool IsLittleEndian,
uint8_t OSABI);
/// createPPCELFObjectWriter - Construct a PPC Mach-O object writer.
/// Construct a PPC Mach-O object writer.
MCObjectWriter *createPPCMachObjectWriter(raw_ostream &OS, bool Is64Bit,
uint32_t CPUType,
uint32_t CPUSubtype);
/// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s with
/// any number of 0s on either side. The 1s are allowed to wrap from LSB to
/// MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is
/// not, since all 1s are not contiguous.
/// Returns true iff Val consists of one contiguous run of 1s with any number of
/// 0s on either side. The 1s are allowed to wrap from LSB to MSB, so
/// 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is not,
/// since all 1s are not contiguous.
static inline bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
if (!Val)
return false;

19
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
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@ -34,7 +34,7 @@ class raw_ostream;
extern Target TheX86_32Target, TheX86_64Target;
/// DWARFFlavour - Flavour of dwarf regnumbers
/// Flavour of dwarf regnumbers
///
namespace DWARFFlavour {
enum {
@ -42,7 +42,7 @@ namespace DWARFFlavour {
};
}
/// N86 namespace - Native X86 register numbers
/// Native X86 register numbers
///
namespace N86 {
enum {
@ -57,9 +57,8 @@ namespace X86_MC {
void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI);
/// createX86MCSubtargetInfo - Create a X86 MCSubtargetInfo instance.
/// This is exposed so Asm parser, etc. do not need to go through
/// TargetRegistry.
/// Create a X86 MCSubtargetInfo instance. This is exposed so Asm parser, etc.
/// do not need to go through TargetRegistry.
MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS);
}
@ -81,24 +80,24 @@ MCStreamer *createX86WinCOFFStreamer(MCContext &C, MCAsmBackend &AB,
raw_ostream &OS, MCCodeEmitter *CE,
bool RelaxAll);
/// createX86MachObjectWriter - Construct an X86 Mach-O object writer.
/// Construct an X86 Mach-O object writer.
MCObjectWriter *createX86MachObjectWriter(raw_ostream &OS,
bool Is64Bit,
uint32_t CPUType,
uint32_t CPUSubtype);
/// createX86ELFObjectWriter - Construct an X86 ELF object writer.
/// Construct an X86 ELF object writer.
MCObjectWriter *createX86ELFObjectWriter(raw_ostream &OS,
bool IsELF64,
uint8_t OSABI,
uint16_t EMachine);
/// createX86WinCOFFObjectWriter - Construct an X86 Win COFF object writer.
/// Construct an X86 Win COFF object writer.
MCObjectWriter *createX86WinCOFFObjectWriter(raw_ostream &OS, bool Is64Bit);
/// createX86_64MachORelocationInfo - Construct X86-64 Mach-O relocation info.
/// Construct X86-64 Mach-O relocation info.
MCRelocationInfo *createX86_64MachORelocationInfo(MCContext &Ctx);
/// createX86_64ELFORelocationInfo - Construct X86-64 ELF relocation info.
/// Construct X86-64 ELF relocation info.
MCRelocationInfo *createX86_64ELFRelocationInfo(MCContext &Ctx);
} // End llvm namespace