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ARM VEXT tighten up operand classes a bit.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145722 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-12-02 22:57:57 +00:00
parent 84defb51ca
commit e40ab244c1
1 changed files with 2 additions and 2 deletions
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4
lib/Target/ARM/ARMInstrNEON.td
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@ -5027,7 +5027,7 @@ def : AlignedVEXTq<v2f32, v4f32, DSubReg_i32_reg>;
class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
: N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
(ins DPR:$Vn, DPR:$Vm, i32imm:$index), NVExtFrm,
(ins DPR:$Vn, DPR:$Vm, imm0_7:$index), NVExtFrm,
IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
[(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
(Ty DPR:$Vm), imm:$index)))]> {
@ -5037,7 +5037,7 @@ class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
: N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
(ins QPR:$Vn, QPR:$Vm, i32imm:$index), NVExtFrm,
(ins QPR:$Vn, QPR:$Vm, imm0_15:$index), NVExtFrm,
IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
[(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
(Ty QPR:$Vm), imm:$index)))]> {