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Sink queries into asserts since the variable is unused otherwise.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227836 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2015-02-02 18:58:24 +00:00
parent ca8d3bf8af
commit e4100fc79e
1 changed files with 2 additions and 3 deletions
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5
lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp
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@ -68,7 +68,6 @@ char HexagonExpandPredSpillCode::ID = 0;
bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
const HexagonSubtarget &QST = Fn.getSubtarget<HexagonSubtarget>();
const HexagonRegisterInfo *TRI = QST.getRegisterInfo();
const HexagonInstrInfo *TII = QST.getInstrInfo();
// Loop over all of the basic blocks.
@ -83,7 +82,7 @@ bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
if (Opc == Hexagon::STriw_pred) {
// STriw_pred [R30], ofst, SrcReg;
unsigned FP = MI->getOperand(0).getReg();
assert(FP == TRI->getFrameRegister() &&
assert(FP == QST.getRegisterInfo()->getFrameRegister() &&
"Not a Frame Pointer, Nor a Spill Slot");
assert(MI->getOperand(1).isImm() && "Not an offset");
int Offset = MI->getOperand(1).getImm();
@ -130,7 +129,7 @@ bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
assert(Hexagon::PredRegsRegClass.contains(DstReg) &&
"Not a predicate register");
unsigned FP = MI->getOperand(1).getReg();
assert(FP == TRI->getFrameRegister() &&
assert(FP == QST.getRegisterInfo()->getFrameRegister() &&
"Not a Frame Pointer, Nor a Spill Slot");
assert(MI->getOperand(2).isImm() && "Not an offset");
int Offset = MI->getOperand(2).getImm();