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MachineInstr: Change return value of getOpcode() to unsigned.

Browse Source 
This was previously returning int. However there are no negative opcode
numbers and more importantly this was needlessly different from
MCInstrDesc::getOpcode() (which even is the value returned here) and
SDValue::getOpcode()/SDNode::getOpcode().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237611 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matthias Braun 2015-05-18 20:27:55 +00:00
parent 881547e01b
commit e4603f0daf
17 changed files with 54 additions and 55 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
include/llvm/CodeGen/MachineInstr.h
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@ -271,9 +271,8 @@ public:
/// MachineInstr.
const MCInstrDesc &getDesc() const { return *MCID; }
/// getOpcode - Returns the opcode of this MachineInstr.
///
int getOpcode() const { return MCID->Opcode; }
/// Returns the opcode of this MachineInstr.
unsigned getOpcode() const { return MCID->Opcode; }
/// Access to explicit operands of the instruction.
///

8
include/llvm/Target/TargetInstrInfo.h
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@ -53,7 +53,7 @@ class TargetInstrInfo : public MCInstrInfo {
TargetInstrInfo(const TargetInstrInfo &) = delete;
void operator=(const TargetInstrInfo &) = delete;
public:
TargetInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1)
TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u)
: CallFrameSetupOpcode(CFSetupOpcode),
CallFrameDestroyOpcode(CFDestroyOpcode) {
}
@ -109,8 +109,8 @@ public:
/// between operating with a frame pointer and operating without, through the
/// use of these two instructions.
///
int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
unsigned getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
unsigned getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
/// Returns the actual stack pointer adjustment made by an instruction
/// as part of a call sequence. By default, only call frame setup/destroy
@ -1244,7 +1244,7 @@ public:
}
private:
int CallFrameSetupOpcode, CallFrameDestroyOpcode;
unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode;
};
} // End llvm namespace

4
lib/CodeGen/MachineVerifier.cpp
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@ -1716,8 +1716,8 @@ namespace {
/// by a FrameDestroy <n>, stack adjustments are identical on all
/// CFG edges to a merge point, and frame is destroyed at end of a return block.
void MachineVerifier::verifyStackFrame() {
int FrameSetupOpcode = TII->getCallFrameSetupOpcode();
int FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
unsigned FrameSetupOpcode = TII->getCallFrameSetupOpcode();
unsigned FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
SmallVector<StackStateOfBB, 8> SPState;
SPState.resize(MF->getNumBlockIDs());

10
lib/CodeGen/PrologEpilogInserter.cpp
View File

@ -248,12 +248,12 @@ void PEI::calculateCallsInformation(MachineFunction &Fn) {
bool AdjustsStack = MFI->adjustsStack();
// Get the function call frame set-up and tear-down instruction opcode
int FrameSetupOpcode = TII.getCallFrameSetupOpcode();
int FrameDestroyOpcode = TII.getCallFrameDestroyOpcode();
unsigned FrameSetupOpcode = TII.getCallFrameSetupOpcode();
unsigned FrameDestroyOpcode = TII.getCallFrameDestroyOpcode();
// Early exit for targets which have no call frame setup/destroy pseudo
// instructions.
if (FrameSetupOpcode == -1 && FrameDestroyOpcode == -1)
if (FrameSetupOpcode == ~0u && FrameDestroyOpcode == ~0u)
return;
std::vector<MachineBasicBlock::iterator> FrameSDOps;
@ -864,8 +864,8 @@ void PEI::replaceFrameIndices(MachineBasicBlock *BB, MachineFunction &Fn,
const TargetInstrInfo &TII = *Fn.getSubtarget().getInstrInfo();
const TargetRegisterInfo &TRI = *Fn.getSubtarget().getRegisterInfo();
const TargetFrameLowering *TFI = Fn.getSubtarget().getFrameLowering();
int FrameSetupOpcode = TII.getCallFrameSetupOpcode();
int FrameDestroyOpcode = TII.getCallFrameDestroyOpcode();
unsigned FrameSetupOpcode = TII.getCallFrameSetupOpcode();
unsigned FrameDestroyOpcode = TII.getCallFrameDestroyOpcode();
if (RS && !FrameIndexVirtualScavenging) RS->enterBasicBlock(BB);

4
lib/CodeGen/ShrinkWrap.cpp
View File

@ -106,9 +106,9 @@ class ShrinkWrap : public MachineFunctionPass {
/// Frequency of the Entry block.
uint64_t EntryFreq;
/// Current opcode for frame setup.
int FrameSetupOpcode;
unsigned FrameSetupOpcode;
/// Current opcode for frame destroy.
int FrameDestroyOpcode;
unsigned FrameDestroyOpcode;
/// Entry block.
const MachineBasicBlock *Entry;

4
lib/CodeGen/TargetInstrInfo.cpp
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@ -652,8 +652,8 @@ int TargetInstrInfo::getSPAdjust(const MachineInstr *MI) const {
bool StackGrowsDown =
TFI->getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown;
int FrameSetupOpcode = getCallFrameSetupOpcode();
int FrameDestroyOpcode = getCallFrameDestroyOpcode();
unsigned FrameSetupOpcode = getCallFrameSetupOpcode();
unsigned FrameDestroyOpcode = getCallFrameDestroyOpcode();
if (MI->getOpcode() != FrameSetupOpcode &&
MI->getOpcode() != FrameDestroyOpcode)

8
lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp
View File

@ -158,7 +158,7 @@ static unsigned getSrcFromCopy(const MachineInstr *MI,
// getTransformOpcode - For any opcode for which there is an AdvSIMD equivalent
// that we're considering transforming to, return that AdvSIMD opcode. For all
// others, return the original opcode.
static int getTransformOpcode(unsigned Opc) {
static unsigned getTransformOpcode(unsigned Opc) {
switch (Opc) {
default:
break;
@ -179,7 +179,7 @@ static int getTransformOpcode(unsigned Opc) {
}
static bool isTransformable(const MachineInstr *MI) {
int Opc = MI->getOpcode();
unsigned Opc = MI->getOpcode();
return Opc != getTransformOpcode(Opc);
}
@ -286,8 +286,8 @@ void AArch64AdvSIMDScalar::transformInstruction(MachineInstr *MI) {
DEBUG(dbgs() << "Scalar transform: " << *MI);
MachineBasicBlock *MBB = MI->getParent();
int OldOpc = MI->getOpcode();
int NewOpc = getTransformOpcode(OldOpc);
unsigned OldOpc = MI->getOpcode();
unsigned NewOpc = getTransformOpcode(OldOpc);
assert(OldOpc != NewOpc && "transform an instruction to itself?!");
// Check if we need a copy for the source registers.

6
lib/Target/AArch64/AArch64ConditionOptimizer.cpp
View File

@ -92,7 +92,7 @@ class AArch64ConditionOptimizer : public MachineFunctionPass {
public:
// Stores immediate, compare instruction opcode and branch condition (in this
// order) of adjusted comparison.
typedef std::tuple<int, int, AArch64CC::CondCode> CmpInfo;
typedef std::tuple<int, unsigned, AArch64CC::CondCode> CmpInfo;
static char ID;
AArch64ConditionOptimizer() : MachineFunctionPass(ID) {}
@ -215,7 +215,7 @@ static AArch64CC::CondCode getAdjustedCmp(AArch64CC::CondCode Cmp) {
// operator and condition code.
AArch64ConditionOptimizer::CmpInfo AArch64ConditionOptimizer::adjustCmp(
MachineInstr *CmpMI, AArch64CC::CondCode Cmp) {
int Opc = CmpMI->getOpcode();
unsigned Opc = CmpMI->getOpcode();
// CMN (compare with negative immediate) is an alias to ADDS (as
// "operand - negative" == "operand + positive")
@ -244,7 +244,7 @@ AArch64ConditionOptimizer::CmpInfo AArch64ConditionOptimizer::adjustCmp(
void AArch64ConditionOptimizer::modifyCmp(MachineInstr *CmpMI,
const CmpInfo &Info) {
int Imm;
int Opc;
unsigned Opc;
AArch64CC::CondCode Cmp;
std::tie(Imm, Opc, Cmp) = Info;

2
lib/Target/AArch64/AArch64FrameLowering.cpp
View File

@ -161,7 +161,7 @@ void AArch64FrameLowering::eliminateCallFramePseudoInstr(
const AArch64InstrInfo *TII =
static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo());
DebugLoc DL = I->getDebugLoc();
int Opc = I->getOpcode();
unsigned Opc = I->getOpcode();
bool IsDestroy = Opc == TII->getCallFrameDestroyOpcode();
uint64_t CalleePopAmount = IsDestroy ? I->getOperand(1).getImm() : 0;

4
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
View File

@ -494,7 +494,7 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
MachineInstr *FirstMI = I;
++MBBI;
int Opc = FirstMI->getOpcode();
unsigned Opc = FirstMI->getOpcode();
bool MayLoad = FirstMI->mayLoad();
bool IsUnscaled = isUnscaledLdst(Opc);
unsigned Reg = FirstMI->getOperand(0).getReg();
@ -954,7 +954,7 @@ bool AArch64LoadStoreOpt::optimizeBlock(MachineBasicBlock &MBB) {
MachineInstr *MI = MBBI;
// Do update merging. It's simpler to keep this separate from the above
// switch, though not strictly necessary.
int Opc = MI->getOpcode();
unsigned Opc = MI->getOpcode();
switch (Opc) {
default:
// Just move on to the next instruction.

4
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -1402,7 +1402,7 @@ ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
const MachineInstr *MI1,
const MachineRegisterInfo *MRI) const {
int Opcode = MI0->getOpcode();
unsigned Opcode = MI0->getOpcode();
if (Opcode == ARM::t2LDRpci ||
Opcode == ARM::t2LDRpci_pic ||
Opcode == ARM::tLDRpci ||
@ -1739,7 +1739,7 @@ llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
}
int llvm::getMatchingCondBranchOpcode(int Opc) {
unsigned llvm::getMatchingCondBranchOpcode(unsigned Opc) {
if (Opc == ARM::B)
return ARM::Bcc;
if (Opc == ARM::tB)

2
lib/Target/ARM/ARMBaseInstrInfo.h
View File

@ -439,7 +439,7 @@ static inline bool isPushOpcode(int Opc) {
/// register by reference.
ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
int getMatchingCondBranchOpcode(int Opc);
unsigned getMatchingCondBranchOpcode(unsigned Opc);
/// Determine if MI can be folded into an ARM MOVCC instruction, and return the
/// opcode of the SSA instruction representing the conditional MI.

6
lib/Target/ARM/ARMConstantIslandPass.cpp
View File

@ -240,8 +240,8 @@ namespace {
MachineInstr *MI;
unsigned MaxDisp : 31;
bool isCond : 1;
int UncondBr;
ImmBranch(MachineInstr *mi, unsigned maxdisp, bool cond, int ubr)
unsigned UncondBr;
ImmBranch(MachineInstr *mi, unsigned maxdisp, bool cond, unsigned ubr)
: MI(mi), MaxDisp(maxdisp), isCond(cond), UncondBr(ubr) {}
};
@ -746,7 +746,7 @@ initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs) {
if (I->isDebugValue())
continue;
int Opc = I->getOpcode();
unsigned Opc = I->getOpcode();
if (I->isBranch()) {
bool isCond = false;
unsigned Bits = 0;

30
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
View File

@ -103,7 +103,7 @@ namespace {
DebugLoc dl, unsigned Base, unsigned WordOffset,
ARMCC::CondCodes Pred, unsigned PredReg);
bool MergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
int Offset, unsigned Base, bool BaseKill, int Opcode,
int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
DebugLoc dl,
ArrayRef<std::pair<unsigned, bool> > Regs,
@ -116,14 +116,14 @@ namespace {
int Offset,
unsigned Base,
bool BaseKill,
int Opcode,
unsigned Opcode,
ARMCC::CondCodes Pred,
unsigned PredReg,
unsigned Scratch,
DebugLoc dl,
SmallVectorImpl<MachineBasicBlock::iterator> &Merges);
void MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex, unsigned Base,
int Opcode, unsigned Size,
unsigned Opcode, unsigned Size,
ARMCC::CondCodes Pred, unsigned PredReg,
unsigned Scratch, MemOpQueue &MemOps,
SmallVectorImpl<MachineBasicBlock::iterator> &Merges);
@ -159,7 +159,7 @@ static bool definesCPSR(const MachineInstr *MI) {
}
static int getMemoryOpOffset(const MachineInstr *MI) {
int Opcode = MI->getOpcode();
unsigned Opcode = MI->getOpcode();
bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD;
unsigned NumOperands = MI->getDesc().getNumOperands();
unsigned OffField = MI->getOperand(NumOperands-3).getImm();
@ -186,7 +186,7 @@ static int getMemoryOpOffset(const MachineInstr *MI) {
return Offset;
}
static int getLoadStoreMultipleOpcode(int Opcode, ARM_AM::AMSubMode Mode) {
static int getLoadStoreMultipleOpcode(unsigned Opcode, ARM_AM::AMSubMode Mode) {
switch (Opcode) {
default: llvm_unreachable("Unhandled opcode!");
case ARM::LDRi12:
@ -274,7 +274,7 @@ static int getLoadStoreMultipleOpcode(int Opcode, ARM_AM::AMSubMode Mode) {
namespace llvm {
namespace ARM_AM {
AMSubMode getLoadStoreMultipleSubMode(int Opcode) {
AMSubMode getLoadStoreMultipleSubMode(unsigned Opcode) {
switch (Opcode) {
default: llvm_unreachable("Unhandled opcode!");
case ARM::LDMIA_RET:
@ -478,7 +478,7 @@ bool
ARMLoadStoreOpt::MergeOps(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
int Offset, unsigned Base, bool BaseKill,
int Opcode, ARMCC::CondCodes Pred,
unsigned Opcode, ARMCC::CondCodes Pred,
unsigned PredReg, unsigned Scratch, DebugLoc dl,
ArrayRef<std::pair<unsigned, bool> > Regs,
ArrayRef<unsigned> ImpDefs) {
@ -730,7 +730,7 @@ void ARMLoadStoreOpt::MergeOpsUpdate(MachineBasicBlock &MBB,
unsigned memOpsBegin, unsigned memOpsEnd,
unsigned insertAfter, int Offset,
unsigned Base, bool BaseKill,
int Opcode,
unsigned Opcode,
ARMCC::CondCodes Pred, unsigned PredReg,
unsigned Scratch,
DebugLoc dl,
@ -829,7 +829,7 @@ void ARMLoadStoreOpt::MergeOpsUpdate(MachineBasicBlock &MBB,
/// load / store multiple instructions.
void
ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
unsigned Base, int Opcode, unsigned Size,
unsigned Base, unsigned Opcode, unsigned Size,
ARMCC::CondCodes Pred, unsigned PredReg,
unsigned Scratch, MemOpQueue &MemOps,
SmallVectorImpl<MachineBasicBlock::iterator> &Merges) {
@ -1110,7 +1110,7 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
unsigned Bytes = getLSMultipleTransferSize(MI);
unsigned PredReg = 0;
ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
int Opcode = MI->getOpcode();
unsigned Opcode = MI->getOpcode();
DebugLoc dl = MI->getDebugLoc();
// Can't use an updating ld/st if the base register is also a dest
@ -1248,7 +1248,7 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
unsigned Base = MI->getOperand(1).getReg();
bool BaseKill = MI->getOperand(1).isKill();
unsigned Bytes = getLSMultipleTransferSize(MI);
int Opcode = MI->getOpcode();
unsigned Opcode = MI->getOpcode();
DebugLoc dl = MI->getDebugLoc();
bool isAM5 = (Opcode == ARM::VLDRD || Opcode == ARM::VLDRS ||
Opcode == ARM::VSTRD || Opcode == ARM::VSTRS);
@ -1406,7 +1406,7 @@ static bool isMemoryOp(const MachineInstr *MI) {
MI->getOperand(1).isUndef())
return false;
int Opcode = MI->getOpcode();
unsigned Opcode = MI->getOpcode();
switch (Opcode) {
default: break;
case ARM::VLDRS:
@ -1597,7 +1597,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
unsigned NumMemOps = 0;
MemOpQueue MemOps;
unsigned CurrBase = 0;
int CurrOpc = -1;
unsigned CurrOpc = ~0u;
unsigned CurrSize = 0;
ARMCC::CondCodes CurrPred = ARMCC::AL;
unsigned CurrPredReg = 0;
@ -1616,7 +1616,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
bool isMemOp = isMemoryOp(MBBI);
if (isMemOp) {
int Opcode = MBBI->getOpcode();
unsigned Opcode = MBBI->getOpcode();
unsigned Size = getLSMultipleTransferSize(MBBI);
const MachineOperand &MO = MBBI->getOperand(0);
unsigned Reg = MO.getReg();
@ -1753,7 +1753,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
}
CurrBase = 0;
CurrOpc = -1;
CurrOpc = ~0u;
CurrSize = 0;
CurrPred = ARMCC::AL;
CurrPredReg = 0;

2
lib/Target/SystemZ/SystemZInstrInfo.cpp
View File

@ -423,7 +423,7 @@ static MachineInstr *getDef(unsigned Reg,
}
// Return true if MI is a shift of type Opcode by Imm bits.
static bool isShift(MachineInstr *MI, int Opcode, int64_t Imm) {
static bool isShift(MachineInstr *MI, unsigned Opcode, int64_t Imm) {
return (MI->getOpcode() == Opcode &&
!MI->getOperand(2).getReg() &&
MI->getOperand(3).getImm() == Imm);

8
lib/Target/X86/X86CallFrameOptimization.cpp
View File

@ -128,8 +128,8 @@ bool X86CallFrameOptimization::isLegal(MachineFunction &MF) {
// This is bad, and breaks SP adjustment.
// So, check that all of the frames in the function are closed inside
// the same block, and, for good measure, that there are no nested frames.
int FrameSetupOpcode = TII->getCallFrameSetupOpcode();
int FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
unsigned FrameSetupOpcode = TII->getCallFrameSetupOpcode();
unsigned FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
for (MachineBasicBlock &BB : MF) {
bool InsideFrameSequence = false;
for (MachineInstr &MI : BB) {
@ -214,7 +214,7 @@ bool X86CallFrameOptimization::runOnMachineFunction(MachineFunction &MF) {
if (!isLegal(MF))
return false;
int FrameSetupOpcode = TII->getCallFrameSetupOpcode();
unsigned FrameSetupOpcode = TII->getCallFrameSetupOpcode();
bool Changed = false;
@ -246,7 +246,7 @@ void X86CallFrameOptimization::collectCallInfo(MachineFunction &MF,
const X86RegisterInfo &RegInfo = *static_cast<const X86RegisterInfo *>(
MF.getSubtarget().getRegisterInfo());
unsigned StackPtr = RegInfo.getStackRegister();
int FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
unsigned FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
// We expect to enter this at the beginning of a call sequence
assert(I->getOpcode() == TII->getCallFrameSetupOpcode());

2
lib/Target/X86/X86FrameLowering.cpp
View File

@ -1986,7 +1986,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
const X86RegisterInfo &RegInfo = *STI.getRegisterInfo();
unsigned StackPtr = RegInfo.getStackRegister();
bool reserveCallFrame = hasReservedCallFrame(MF);
int Opcode = I->getOpcode();
unsigned Opcode = I->getOpcode();
bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
bool IsLP64 = STI.isTarget64BitLP64();
DebugLoc DL = I->getDebugLoc();