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https://github.com/c64scene-ar/llvm-6502.git
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Spiller may unfold load / mod / store instructions as an optimization when the would be loaded value is available in a register. It needs to check if it's legal to clobber the register. Also, the register can contain values of multiple spill slots, make sure to check all instead of just the one being unfolded.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67068 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
7ea02ffe91
commit
e47b0089d9
@ -28,6 +28,7 @@ STATISTIC(NumReMats , "Number of re-materialization");
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STATISTIC(NumLoads , "Number of loads added");
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STATISTIC(NumReused , "Number of values reused");
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STATISTIC(NumDCE , "Number of copies elided");
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STATISTIC(NumSUnfold , "Number of stores unfolded");
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namespace {
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enum SpillerName { simple, local };
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@ -1172,8 +1173,8 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM,
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// Okay, we have a two address operand. We can reuse this physreg as
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// long as we are allowed to clobber the value and there isn't an
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// earlier def that has already clobbered the physreg.
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CanReuse = Spills.canClobberPhysReg(ReuseSlot) &&
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!ReusedOperands.isClobbered(PhysReg);
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CanReuse = !ReusedOperands.isClobbered(PhysReg) &&
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Spills.canClobberPhysReg(PhysReg);
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}
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if (CanReuse) {
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@ -1408,6 +1409,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM,
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DOUT << "Removing now-noop copy: " << MI;
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// Unset last kill since it's being reused.
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InvalidateKill(InReg, RegKills, KillOps);
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Spills.disallowClobberPhysReg(InReg);
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}
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InvalidateKills(MI, RegKills, KillOps);
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@ -1446,6 +1448,8 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM,
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// the value and there isn't an earlier def that has already clobbered
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// the physreg.
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if (PhysReg &&
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!ReusedOperands.isClobbered(PhysReg) &&
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Spills.canClobberPhysReg(PhysReg) &&
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!TII->isStoreToStackSlot(&MI, SS)) { // Not profitable!
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MachineOperand *KillOpnd =
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DeadStore->findRegisterUseOperand(PhysReg, true);
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@ -1453,7 +1457,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM,
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// super-register is needed below.
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if (KillOpnd && !KillOpnd->getSubReg() &&
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TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, true,NewMIs)){
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MBB.insert(MII, NewMIs[0]);
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MBB.insert(MII, NewMIs[0]);
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NewStore = NewMIs[1];
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MBB.insert(MII, NewStore);
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VRM.addSpillSlotUse(SS, NewStore);
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@ -1465,6 +1469,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM,
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--NextMII; // backtrack to the unfolded instruction.
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BackTracked = true;
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isDead = true;
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++NumSUnfold;
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}
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}
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}
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@ -1519,7 +1524,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM,
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// If the stack slot value was previously available in some other
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// register, change it now. Otherwise, make the register
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// available in PhysReg.
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Spills.addAvailable(StackSlot, SrcReg, false/*!clobber*/);
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Spills.addAvailable(StackSlot, SrcReg, MI.killsRegister(SrcReg));
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}
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}
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}
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@ -127,15 +127,31 @@ namespace llvm {
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DOUT << " in physreg " << TRI->getName(Reg) << "\n";
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}
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/// canClobberPhysReg - Return true if the spiller is allowed to change the
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/// value of the specified stackslot register if it desires. The specified
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/// stack slot must be available in a physreg for this query to make sense.
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bool canClobberPhysReg(int SlotOrReMat) const {
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/// canClobberPhysRegForSS - Return true if the spiller is allowed to change
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/// the value of the specified stackslot register if it desires. The
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/// specified stack slot must be available in a physreg for this query to
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/// make sense.
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bool canClobberPhysRegForSS(int SlotOrReMat) const {
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assert(SpillSlotsOrReMatsAvailable.count(SlotOrReMat) &&
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"Value not available!");
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return SpillSlotsOrReMatsAvailable.find(SlotOrReMat)->second & 1;
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}
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/// canClobberPhysReg - Return true if the spiller is allowed to clobber the
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/// physical register where values for some stack slot(s) might be
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/// available.
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bool canClobberPhysReg(unsigned PhysReg) const {
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std::multimap<unsigned, int>::const_iterator I =
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PhysRegsAvailable.lower_bound(PhysReg);
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while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
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int SlotOrReMat = I->second;
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I++;
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if (!canClobberPhysRegForSS(SlotOrReMat))
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return false;
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}
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return true;
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}
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/// disallowClobberPhysReg - Unset the CanClobber bit of the specified
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/// stackslot register. The register is still available but is no longer
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/// allowed to be modifed.
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@ -305,4 +321,4 @@ namespace llvm {
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};
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}
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#endif
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#endif
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167
test/CodeGen/X86/2009-03-16-SpillerBug.ll
Normal file
167
test/CodeGen/X86/2009-03-16-SpillerBug.ll
Normal file
@ -0,0 +1,167 @@
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; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -stats |& grep spiller | not grep {stores unfolded}
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; rdar://6682365
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; Do not clobber a register if another spill slot is available in it and it's marked "do not clobber".
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%struct.CAST_KEY = type { [32 x i32], i32 }
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@CAST_S_table0 = constant [2 x i32] [i32 821772500, i32 -1616838901], align 32 ; <[2 x i32]*> [#uses=0]
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@CAST_S_table4 = constant [2 x i32] [i32 2127105028, i32 745436345], align 32 ; <[2 x i32]*> [#uses=6]
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@CAST_S_table5 = constant [2 x i32] [i32 -151351395, i32 749497569], align 32 ; <[2 x i32]*> [#uses=5]
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@CAST_S_table6 = constant [2 x i32] [i32 -2048901095, i32 858518887], align 32 ; <[2 x i32]*> [#uses=4]
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@CAST_S_table7 = constant [2 x i32] [i32 -501862387, i32 -1143078916], align 32 ; <[2 x i32]*> [#uses=5]
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@CAST_S_table1 = constant [2 x i32] [i32 522195092, i32 -284448933], align 32 ; <[2 x i32]*> [#uses=0]
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@CAST_S_table2 = constant [2 x i32] [i32 -1913667008, i32 637164959], align 32 ; <[2 x i32]*> [#uses=0]
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@CAST_S_table3 = constant [2 x i32] [i32 -1649212384, i32 532081118], align 32 ; <[2 x i32]*> [#uses=0]
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define void @CAST_set_key(%struct.CAST_KEY* nocapture %key, i32 %len, i8* nocapture %data) nounwind ssp {
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bb1.thread:
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%0 = getelementptr [16 x i32]* null, i32 0, i32 5 ; <i32*> [#uses=1]
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%1 = getelementptr [16 x i32]* null, i32 0, i32 8 ; <i32*> [#uses=1]
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%2 = load i32* null, align 4 ; <i32> [#uses=1]
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%3 = shl i32 %2, 24 ; <i32> [#uses=1]
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%4 = load i32* null, align 4 ; <i32> [#uses=1]
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%5 = shl i32 %4, 16 ; <i32> [#uses=1]
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%6 = load i32* null, align 4 ; <i32> [#uses=1]
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%7 = or i32 %5, %3 ; <i32> [#uses=1]
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%8 = or i32 %7, %6 ; <i32> [#uses=1]
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%9 = or i32 %8, 0 ; <i32> [#uses=1]
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%10 = load i32* null, align 4 ; <i32> [#uses=1]
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%11 = shl i32 %10, 24 ; <i32> [#uses=1]
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%12 = load i32* %0, align 4 ; <i32> [#uses=1]
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%13 = shl i32 %12, 16 ; <i32> [#uses=1]
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%14 = load i32* null, align 4 ; <i32> [#uses=1]
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%15 = or i32 %13, %11 ; <i32> [#uses=1]
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%16 = or i32 %15, %14 ; <i32> [#uses=1]
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%17 = or i32 %16, 0 ; <i32> [#uses=1]
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br label %bb11
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bb11: ; preds = %bb11, %bb1.thread
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%18 = phi i32 [ %110, %bb11 ], [ 0, %bb1.thread ] ; <i32> [#uses=1]
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%19 = phi i32 [ %112, %bb11 ], [ 0, %bb1.thread ] ; <i32> [#uses=0]
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%20 = phi i32 [ 0, %bb11 ], [ 0, %bb1.thread ] ; <i32> [#uses=0]
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%21 = phi i32 [ %113, %bb11 ], [ 0, %bb1.thread ] ; <i32> [#uses=1]
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%X.0.0 = phi i32 [ %9, %bb1.thread ], [ %92, %bb11 ] ; <i32> [#uses=0]
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%X.1.0 = phi i32 [ %17, %bb1.thread ], [ 0, %bb11 ] ; <i32> [#uses=0]
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%22 = getelementptr [2 x i32]* @CAST_S_table6, i32 0, i32 %21 ; <i32*> [#uses=0]
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%23 = getelementptr [2 x i32]* @CAST_S_table5, i32 0, i32 %18 ; <i32*> [#uses=0]
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%24 = load i32* null, align 4 ; <i32> [#uses=1]
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%25 = xor i32 0, %24 ; <i32> [#uses=1]
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%26 = xor i32 %25, 0 ; <i32> [#uses=1]
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%27 = xor i32 %26, 0 ; <i32> [#uses=4]
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%28 = and i32 %27, 255 ; <i32> [#uses=2]
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%29 = lshr i32 %27, 8 ; <i32> [#uses=1]
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%30 = and i32 %29, 255 ; <i32> [#uses=2]
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%31 = lshr i32 %27, 16 ; <i32> [#uses=1]
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%32 = and i32 %31, 255 ; <i32> [#uses=1]
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%33 = getelementptr [2 x i32]* @CAST_S_table4, i32 0, i32 %28 ; <i32*> [#uses=1]
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%34 = load i32* %33, align 4 ; <i32> [#uses=2]
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%35 = getelementptr [2 x i32]* @CAST_S_table5, i32 0, i32 %30 ; <i32*> [#uses=1]
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%36 = load i32* %35, align 4 ; <i32> [#uses=2]
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%37 = xor i32 %34, 0 ; <i32> [#uses=1]
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%38 = xor i32 %37, %36 ; <i32> [#uses=1]
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%39 = xor i32 %38, 0 ; <i32> [#uses=1]
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%40 = xor i32 %39, 0 ; <i32> [#uses=1]
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%41 = xor i32 %40, 0 ; <i32> [#uses=3]
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%42 = lshr i32 %41, 8 ; <i32> [#uses=1]
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%43 = and i32 %42, 255 ; <i32> [#uses=2]
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%44 = lshr i32 %41, 16 ; <i32> [#uses=1]
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%45 = and i32 %44, 255 ; <i32> [#uses=1]
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%46 = getelementptr [2 x i32]* @CAST_S_table4, i32 0, i32 %43 ; <i32*> [#uses=1]
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%47 = load i32* %46, align 4 ; <i32> [#uses=1]
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%48 = load i32* null, align 4 ; <i32> [#uses=1]
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%49 = xor i32 %47, 0 ; <i32> [#uses=1]
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%50 = xor i32 %49, %48 ; <i32> [#uses=1]
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%51 = xor i32 %50, 0 ; <i32> [#uses=1]
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%52 = xor i32 %51, 0 ; <i32> [#uses=1]
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%53 = xor i32 %52, 0 ; <i32> [#uses=2]
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%54 = and i32 %53, 255 ; <i32> [#uses=1]
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%55 = lshr i32 %53, 24 ; <i32> [#uses=1]
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%56 = getelementptr [2 x i32]* @CAST_S_table6, i32 0, i32 %55 ; <i32*> [#uses=1]
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%57 = load i32* %56, align 4 ; <i32> [#uses=1]
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%58 = xor i32 0, %57 ; <i32> [#uses=1]
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%59 = xor i32 %58, 0 ; <i32> [#uses=1]
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%60 = xor i32 %59, 0 ; <i32> [#uses=1]
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store i32 %60, i32* null, align 4
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%61 = getelementptr [2 x i32]* @CAST_S_table4, i32 0, i32 0 ; <i32*> [#uses=1]
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%62 = load i32* %61, align 4 ; <i32> [#uses=1]
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%63 = getelementptr [2 x i32]* @CAST_S_table7, i32 0, i32 %54 ; <i32*> [#uses=1]
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%64 = load i32* %63, align 4 ; <i32> [#uses=1]
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%65 = xor i32 0, %64 ; <i32> [#uses=1]
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%66 = xor i32 %65, 0 ; <i32> [#uses=1]
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store i32 %66, i32* null, align 4
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%67 = getelementptr [2 x i32]* @CAST_S_table7, i32 0, i32 %45 ; <i32*> [#uses=1]
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%68 = load i32* %67, align 4 ; <i32> [#uses=1]
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%69 = xor i32 %36, %34 ; <i32> [#uses=1]
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%70 = xor i32 %69, 0 ; <i32> [#uses=1]
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%71 = xor i32 %70, %68 ; <i32> [#uses=1]
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%72 = xor i32 %71, 0 ; <i32> [#uses=1]
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store i32 %72, i32* null, align 4
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%73 = getelementptr [2 x i32]* @CAST_S_table4, i32 0, i32 %32 ; <i32*> [#uses=1]
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%74 = load i32* %73, align 4 ; <i32> [#uses=2]
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%75 = load i32* null, align 4 ; <i32> [#uses=1]
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%76 = getelementptr [2 x i32]* @CAST_S_table6, i32 0, i32 %43 ; <i32*> [#uses=1]
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%77 = load i32* %76, align 4 ; <i32> [#uses=1]
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%78 = getelementptr [2 x i32]* @CAST_S_table7, i32 0, i32 0 ; <i32*> [#uses=1]
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%79 = load i32* %78, align 4 ; <i32> [#uses=1]
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%80 = getelementptr [2 x i32]* @CAST_S_table7, i32 0, i32 %30 ; <i32*> [#uses=1]
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%81 = load i32* %80, align 4 ; <i32> [#uses=2]
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%82 = xor i32 %75, %74 ; <i32> [#uses=1]
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%83 = xor i32 %82, %77 ; <i32> [#uses=1]
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%84 = xor i32 %83, %79 ; <i32> [#uses=1]
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%85 = xor i32 %84, %81 ; <i32> [#uses=1]
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store i32 %85, i32* null, align 4
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%86 = getelementptr [2 x i32]* @CAST_S_table5, i32 0, i32 %28 ; <i32*> [#uses=1]
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%87 = load i32* %86, align 4 ; <i32> [#uses=1]
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%88 = xor i32 %74, %41 ; <i32> [#uses=1]
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%89 = xor i32 %88, %87 ; <i32> [#uses=1]
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%90 = xor i32 %89, 0 ; <i32> [#uses=1]
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%91 = xor i32 %90, %81 ; <i32> [#uses=1]
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%92 = xor i32 %91, 0 ; <i32> [#uses=3]
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%93 = lshr i32 %92, 16 ; <i32> [#uses=1]
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%94 = and i32 %93, 255 ; <i32> [#uses=1]
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store i32 %94, i32* null, align 4
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%95 = lshr i32 %92, 24 ; <i32> [#uses=2]
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%96 = getelementptr [2 x i32]* @CAST_S_table4, i32 0, i32 %95 ; <i32*> [#uses=1]
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%97 = load i32* %96, align 4 ; <i32> [#uses=1]
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%98 = getelementptr [2 x i32]* @CAST_S_table5, i32 0, i32 0 ; <i32*> [#uses=1]
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%99 = load i32* %98, align 4 ; <i32> [#uses=1]
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%100 = load i32* null, align 4 ; <i32> [#uses=0]
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%101 = xor i32 %97, 0 ; <i32> [#uses=1]
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%102 = xor i32 %101, %99 ; <i32> [#uses=1]
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%103 = xor i32 %102, 0 ; <i32> [#uses=1]
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%104 = xor i32 %103, 0 ; <i32> [#uses=0]
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store i32 0, i32* null, align 4
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%105 = xor i32 0, %27 ; <i32> [#uses=1]
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%106 = xor i32 %105, 0 ; <i32> [#uses=1]
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%107 = xor i32 %106, 0 ; <i32> [#uses=1]
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%108 = xor i32 %107, 0 ; <i32> [#uses=1]
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%109 = xor i32 %108, %62 ; <i32> [#uses=3]
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%110 = and i32 %109, 255 ; <i32> [#uses=1]
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%111 = lshr i32 %109, 16 ; <i32> [#uses=1]
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%112 = and i32 %111, 255 ; <i32> [#uses=1]
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%113 = lshr i32 %109, 24 ; <i32> [#uses=3]
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store i32 %113, i32* %1, align 4
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%114 = load i32* null, align 4 ; <i32> [#uses=1]
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%115 = xor i32 0, %114 ; <i32> [#uses=1]
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%116 = xor i32 %115, 0 ; <i32> [#uses=1]
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%117 = xor i32 %116, 0 ; <i32> [#uses=1]
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%K.0.sum42 = or i32 0, 12 ; <i32> [#uses=1]
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%118 = getelementptr [32 x i32]* null, i32 0, i32 %K.0.sum42 ; <i32*> [#uses=1]
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store i32 %117, i32* %118, align 4
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%119 = getelementptr [2 x i32]* @CAST_S_table5, i32 0, i32 0 ; <i32*> [#uses=0]
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store i32 0, i32* null, align 4
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%120 = getelementptr [2 x i32]* @CAST_S_table6, i32 0, i32 %113 ; <i32*> [#uses=1]
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%121 = load i32* %120, align 4 ; <i32> [#uses=1]
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%122 = xor i32 0, %121 ; <i32> [#uses=1]
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store i32 %122, i32* null, align 4
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%123 = getelementptr [2 x i32]* @CAST_S_table4, i32 0, i32 0 ; <i32*> [#uses=1]
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%124 = load i32* %123, align 4 ; <i32> [#uses=1]
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%125 = getelementptr [2 x i32]* @CAST_S_table7, i32 0, i32 %95 ; <i32*> [#uses=1]
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%126 = load i32* %125, align 4 ; <i32> [#uses=1]
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%127 = xor i32 0, %124 ; <i32> [#uses=1]
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%128 = xor i32 %127, 0 ; <i32> [#uses=1]
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%129 = xor i32 %128, %126 ; <i32> [#uses=1]
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%130 = xor i32 %129, 0 ; <i32> [#uses=1]
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store i32 %130, i32* null, align 4
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br label %bb11
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}
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